View ISL94203EVKIT1Z_8393877.PDF datasheet online --- IC-ON-LINE

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1 datasheet 3-to-8 cell li-ion battery pack monitor isl94203 the isl94203 is a li-ion battery monitor ic that supports from 3 to 8 series connected cells. it provides full battery monitoring and pack control. the isl94203 provides automatic shutdown and recovery from out of bounds conditions and automatically controls pack cell balancing. the isl94203 is highly configurab le as a stand-alone unit, but can be used with an external microcontroller, which communicates to the ic through an i 2 c interface. applications ?power tools ? battery back-up systems ?e-bikes features ? eight cell voltage monitors support li-ion coo 2 , li-ion mn 2 o 4 and li-ion fepo4 chemistries ? stand-alone pack control - no microcontroller needed ? multiple voltage pr otection options (each programmable to 4.8v; 12-bit digital value) and selectable overcurrent protection levels ? programmable detection/recovery times for overvoltage, undervoltage, overcurrent and short circuit conditions ? configuration/calibration registers maintained in eeprom ? open battery connect detection ? integrated charge/discharge fet drive circuitry with built-in charge pump supports high-side n-channel fets ? cell balancing uses external fets with internal state machine or external microcontroller ? enters low power states after periods of inactivity. charge or discharge current detection resumes normal scan rates gnd chrg p+ p- vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 isl94203 vss cs1 cs2 cfet pcfet vdd dfet ldmon chmon vbatt rgo vref scl sda sd eoc int fetsoff psd tempo xt1 xt2 addr c2 c3 c1 43v 43v figure 1. typical application diagram caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc. 2012, 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. august 17, 2015 fn7626.4
isl94203 2 fn7626.4 august 17, 2015 submit document feedback table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 symbol table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 external temperature configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 wake-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 change in fet control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 automatic temperature scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 serial interface timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 discharge overcurrent/short-circ uit monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 charge overcurrent monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 battery connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 power path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pack configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 battery cell connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 power-up operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 wake-up circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 low power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 typical operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 cell fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 open wire detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 current and voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 current sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 overcurrent and short-circ uit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 overcurrent and short-circ uit response (discharge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 overcurrent response (charge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 microcontroller overcurrent fet control protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 voltage, temperature and current scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 cell voltage monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 overvoltage detection/response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 undervoltage detection/response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 temperature monitoring/response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 microcontroller read of voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 voltage conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 microcontroller fet control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 cell balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 cell balance in cascade mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 c control of cell balance fets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 cell balance fet drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 power fet drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 general i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 higher voltage microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 packs with fewer than 8 cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
isl94203 3 fn7626.4 august 17, 2015 submit document feedback pc board layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 qfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 circuit diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 serial interface conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 clock and data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 synchronizing microcontroller operations with internal scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 registers: summary (eeprom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 registers: summary (ram). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 registers: detailed (eeprom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 registers: detailed (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
isl94203 4 fn7626.4 august 17, 2015 submit document feedback pin configuration isl94203 (48 ld tqfn) top view ordering information part number ( notes 2 , 3 )quantity part marking temp. range (c) package (rohs compliant) pkg. dwg. # isl94203irtz bulk quantity 94203 irtz -40 to +85 48 ld tqfn l48.6x6 isl94203irtz-t7 ( note 1 ) 1000/reel 94203 irtz -40 to +85 48 ld tqfn l48.6x6 isl94203irtz-t ( note 1 ) 4000/reel 94203 irtz -40 to +85 48 ld tqfn l48.6x6 ISL94203EVKIT1Z one evaluation kit notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is rohs complian t and compatible with both snpb and pb-free soldering operation s). intersil pb-free products are msl classified at pb-free peak reflow temperatures th at meet or exceed the pb-free requirements of ipc/jedec j std -020. 3. for moisture sensitivity level (msl), please see device information page for isl94203 . for more information on msl please see tech brief tb363 . vbatt csi1 csi2 cfet 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 pcfet vdd dfet c1 c2 c3 ldmon chmon vc2 cb2 vc1 cb1 vc0 vss vref xt1 xt2 tempo dnc addr vss rgo eoc sd fetsoff psd int dnc vss sdao sdai scl vc8 cb8 vc7 cb7 vc6 cb6 vc5 cb5 vc4 cb4 vc3 cb3 pad
isl94203 5 fn7626.4 august 17, 2015 submit document feedback pin descriptions pin number symbol description 1, 3, 5, 7, 9, 11, 13, 15, 17 vc8, vc7, vc6, vc5, vc4, vc3, vc2, vc1, vc0 battery cell n voltage input. this pin is used to monitor the voltage of this battery cell. the voltage is level shifted to a ground reference and is monitored internally by an adc converter. vc n connects to the positive term inal of a battery cell (celln) and vc(n-1) the negative terminal of celln (vss co nnects with the negative terminal of cell1). 2, 4, 6, 8, 10, 12, 14, 16 cb8, cb7, cb6, cb5, cb4, cb3, cb2, cb1 cell balancing fet control output n. this internal drive circuit controls an external fet used to divert a portion of the current around a cell while the cell is being charged or adds to the curre nt pulled from a cell during discharge in order to perform a cell voltage balancing operation. this function is generally used to reduce the voltage on an individual cell relative to other cells in the pack. the cell balancing fets are turned on or of f by an internal cell balance state machine or an external controller. 18, 28, 29 vss ground . this pin connects to the most nega tive terminal in the battery string. 19 vref voltage reference output. this output provides a 1.8v reference voltage for the internal circuitry and for the external microcontroller. 20, 21 xt1, xt2 temperature monitor inputs. these pins input the voltage across two external thermistors used to determine the temperature of the cells and or the power fet. when this in put drops below the threshold, an external over-temperature condition exists. 22 tempo temperature monitor output control. this pin outputs a voltage to be used in a divider that consists of a fixed resistor and a thermistor. the thermistor is located in close proximity to the cells or the power fet. the tempo output is connected internally to the vref voltage through a pmos switch only during a measurement of the temperature, otherwise the tempo output is off. 23, 30 dnc do not connect 24 addr serial address. this is an address input for an i 2 c communication link to allow for two cascaded devices on one bus. 25 scl serial clock. this is the clock input for an i 2 c communication link. 26, 27 sdai, sdao serial data. these are the data lines for an i 2 c interface. when connected together they form the standard bidirectional interface for the i 2 c bus. when separated, they can use separate level shifters for a cascaded operation. 31 int interrupt. this pin goes active low, when there is an external c connected to the isl94203 and c communication fails to send a slave byte within a watchdog timer period. this is a cmos type output. 32 psd pack shutdown. this pin goes active high, when any cell voltage reac hes the ovlo threshold (ovlo flag). optionally, psd is also set if there is a voltage differential between any two cells that is greater than a specified limit (cellf flag) or if the re is an open wire condition. this pin can be used for blowing a fuse in the pack or as an interrupt to an external c. 33 fetsoff fetsoff. this input allows an external microcontroller to turn off both power fet and cb outputs. this pin should be pulled low when inactive. 34 sd shutdown. this output indicates that the isl94203 detected any fail ure condition that would result in the dfet turning off. this could be undervoltage, overcurrent, over - temperature, under-temperature, etc. the sd pin also goes active if there is any charge overcurrent condition. this is an open drain output. 35 eoc end-of-charge. this output indicates that the isl94203 detected a fully charged condition. this is defined by any cell voltage exceeding an eoc voltage (as defined by an eoc value in eeprom). 36 rgo regulator output. this is the 2.5v regulator output. 37 chmon charge monitor. this input monitors the charger conn ection. when the ic is in the sleep mode, connecting this pin to the charger wakes up the device. when the ic recovers from a charge overcurrent condition, this pin is used to monitor that the charger is removed prior to turning on the power fets. in a single path configuration, this pin and the ldmon pin connect together. 38 ldmon load monitor. this pin monitors the load connection. when the ic is in the sleep mode, connecting this pin to a load wakes up the device. when the ic recovers from a discharge overcurrent or short circuit condition, this pin is used to monitor that the load is removed prior to turning on the power fets. in a single path configuration, this pin and the chmon pin connect together. 39, 40, 41 c3, c2, c1 charge pump capacitor pins. these external capacitors are used for the charge pump driving the power fets.
isl94203 6 fn7626.4 august 17, 2015 submit document feedback 42 dfet discharge fet control. the isl94203 controls the gate of a discharge fet through this pin. the power fet is an n-channel device. the fet is turned on by the isl 94203 if all conditions are acceptable. the isl94203 will turn off the fet in the event of an out of bounds condition. the fet can be turned off by an external microcontroller by writing to the cfet control bit. the cfet output is also turned off by the fetsoff pin. the fet output cannot be turned on by an external microcontroller if there are any out of bounds conditions. 43 vdd ic supply pin. this pin provides the operating voltage for the ic circuitry. 44 pcfet precharge fet control. the isl94203 controls the gate of a precharge fet through this pin. the power fet is an n-channel device. the fet is turned on by the isl 94203 if all conditions are acceptable. the isl94203 will turn off the fet in the event of an out of bounds condition. the fet can be turned off by an external microcontroller by writing to the pcfet control bit. the pcfet output is also turned off by the fetsoff pin. the fe t output cannot be turned on by an external microcontroller if there are any out of bounds conditions. either the pcfet or the cfet turn on, but not both. 45 cfet charge fet control. the isl94203 controls the gate of a charge fet thro ugh this pin. the power fet is an n-channel device. the fet is turned on by the isl94203 if all conditions are acce ptable. the isl94203 will turn of f the fet in the event of an out of bounds condition. the fet can be turned off by an extern al microcontroller by writing to the cfet control bit. the cfet output is also turned off by the fetsoff pin. the fet output ca nnot be turned on by an external microcontroller if there are any out of bounds conditions. either the pcfet or the cfet turn on, but not both. 46, 47 csi2, csi1 current sense inputs. these pins connect to the isl94203 current sense ci rcuit. there is an external resistance across which the circuit operates. the sense resi stor is typically in the range of 0.2m to 5m . 48 vbatt input level shifter supply and battery pack voltage input. this pin powers the input level shifters and is also used to monitor the voltage of the battery stack. the voltage is internally di vided by 32 and connected to an adc converter through a mux. pad gnd thermal pad. this pad should connect to ground. pin descriptions (continued) pin number symbol description
isl94203 7 fn7626.4 august 17, 2015 submit document feedback osc p+ p- 1k ? 1k ? 1k ? 47nf 47nf 47nf 1k ? 47nf 1k ? 47nf 47nf 1k ? 47nf 1k ? cs1 cs2 ram eeprom sd vss eoc vss pack- pack+ bat+ bat- vb/16 rgo/2 cb1 cb2 cb3 cb4 cb5 cb6 cb7 20k ? 20k ? 20k ? 20k ? 20k ? rgo 1k ? 47nf cb8 20k ? fet controls/charge pump cfet dfet ldmon o.c. recovery wakeup circuit n-channel fets vdd sdai scl fetsoff tempo registers addr sdao xt2 xt1 input buffer/level shifter/open wire detect vc6 vc3 vc4 vc5 vc7 vc1 vc2 vc0 vc8 rgo (out) reg ldo current sense gain amplifier x5/x50/x500 gain chmon cb state cb8:1 pcfet i 2 c power on machine reset state machine timing and control memory manager scan state cb state overcurrent state eoc/sd/error state temp/voltage monitor alu figure 2. block diagram overcurrent state machine vdd vdd psd v ss c1 c2 c3 vref vref int vbatt 100 ? 470nf mux mux xt2 xt1 temp 14-bit scan state machine +16v +16v 20k ? 20k ? adc 330k ? 10k ? 330k ? 10k ? 330k ? 10k ? 10k ? 10k ? 10k ? 10k ? 10k ? 330k ? 330k ? 330k ? 330k ? 330k ? eoc/sd error conditions (ov, uv, slp state machines) watchdog timer it temp t gain mux x1/x2
isl94203 8 fn7626.4 august 17, 2015 submit document feedback absolute maximum ratings ( note 4 ) thermal information power supply voltage, v dd . . . . . . . . . . . . . . . . . v ss -0.5v to v ss + 45.0v cell voltage (vc, vbatt) vcn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v batt + 0.5v vcn - vss (n = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 45.0v vcn - vss (n = 6, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 36.0v vcn - vss (n = 4, 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to 27.0v vcn - vss (n = 2, 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to 17.0v vcn - vss (n = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to 7.0v vcn - vss (n = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 3.0v vcn - vc(n-1) (n = 2 to 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-3.0v to 7.0v vc1 - vc0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to 7.0v cell balance pin voltages (vcb) vcbn - vcn-1, n = 1 to 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to 7.0v vcn - vcbn, n = 6 to 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to 7.0v terminal voltage addr, xt1, xt2, fetsoff, psd, int . . . . . . . . . . . . . . -0.5 to v rgo +0.5v scl, sdai, sdao, eoc , sd . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to 5.5v cfet, pcfet, c1, c2, c3 . . . . . . . v dd - 0.5v to v dd + 15.5v (60v max) dfet, chmon, ldmon . . . . . . . . . . . . . . -0.5v to v dd + 15.0v (60v max) current sense voltage vbatt, cs1, cs2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd +1.0v vbatt - cs1, vbatt - cs2 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +0.5v cs1 - cs2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +0.5v esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 2kv charged device model (tested per jesd22-c101f). . . . . . . . . . . . . . 1kv latch-up (tested per jesd-78d; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 48 ld qfn ( notes 5 , 6 ) . . . . . . . . . . . . . . . . 28 0.75 continuous package power dissipation. . . . . . . . . . . . . . . . . . . . . . . .400mw maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c operating voltage: v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4v to 36v vcn-vc(n-1) specified range . . . . . . . . . . . . . . . . . . . . . . . . . 2.0v to 4.3v vcn-vc(n-1) extended range . . . . . . . . . . . . . . . . . . . . . . . . . 1.0v to 4.4v vcn-vc(n-1) maximum range (any cell) . . . . . . . . . . . . . . . . 0.5v to 4.8v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. devices are characterized, but not producti on tested, at absolute maximum voltages. 5. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v dd = 26.4v, t a = -40c to +85c, unless otherwise specified. boldface specification limits apply across operating temperature range, -40c to +85c. parameter symbol test condition min ( note 7 )typ max ( note 7 )units power-up condition ? threshold rising (device becomes operational) v porr1 v dd minimum voltage at which device operation begins (cfet turns on; chmon = v dd ) 6.0 v v porr2 chmon minimum voltage at which device operation begins (cfet turns on; v dd > 6.0v) vdd v power-down condition ? threshold falling v porf v dd minimum voltage device remains operational (rgo turns off) 3.0 v 2.5v regulated voltage v rgo i rgo = 3ma 2.4 2.5 2.6 v 1.8v reference voltage v ref 1.79 1.8 1.81 v vbatt input current - v batt i vbatt input current; normal/idle/doze v dd = 33.6v 38 45 a input current; sleep/power-down v dd = 33.6v 1 a
isl94203 9 fn7626.4 august 17, 2015 submit document feedback v dd supply current i vdd1 device active (normal mode) (no error conditions) cfet, pcfet, dfet = off; v dd = 33.6v 310 370 a i vdd2 device active (idle mode) (no error conditions) idle = 1 cfet, pcfet, dfet = off; v dd = 33.6v 215 275 a i vdd3 device active (doze mode) (no error conditions) doze = 1 cfet, pcfet, dfet = off; v dd = 33.6v 210 265 a i vdd4 fet drive current (i vdd increase when fets are on - normal/idle/doze modes); v dd = 33.6v 215 a i vdd5 device active (sleep mode); sleep = 1; v dd = 33.6v 0c to +60c -40c to +85c 13 30 50 a i vdd6 power-down pdwn = 1; v dd = 33.6v 1 a input bias current ics1 v dd = v batt = vcs1 = vcs2 = 33.6v (normal, idle, doze) 10 15 a v dd = v batt = vcs1 = vcs2 = 33.6v (sleep, power-down) 0c to +60c -40c to +85c 1 3 a ics2 v dd = v batt = vcs1 = vcs2 = 33.6v (normal, idle, doze) 10 15 a v dd = v batt = vcs1 = vcs2 = 33.6v (sleep, power-down) 0c to +60c -40c to +85c 1 3 a vcn input current i vcn cell input leakage current ao2:ao0 = 0000h (normal/idle/doze; not sampling cells) -1 1 a cbn input current i cbn cell balance pin leakage current (no balance active) -1 1 a temperature monitor specifications external temperature accuracy v xt1 external temperature monitoring error. adc voltage error when monitoring xt1 input. tgain = 0; (xtn = 0.2v to 0.737v) -25 15 mv internal temperature monitor output (see ? temperature monitoring/response ? on page 35 ) t int25 [itb:it0] 10 *1.8/4095/gain gain = 2 (tgain bit = 0) temperature = +25c 0.276 v v intmon change in [itb:it0] 10 *1.8/4095/gain gain = 2 (tgain bit = 0) temperature = -40c to +85c 1.0 mv/c electrical specifications v dd = 26.4v, t a = -40c to +85c, unless otherwise specified. boldface specification limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test condition min ( note 7 )typ max ( note 7 )units
isl94203 10 fn7626.4 august 17, 2015 submit document feedback cell voltage monitor specifications cell monitor voltage accuracy v adcr relative cell measurement error (max absolute cell measurement error - min absolute cell measurement error) vcn - vc(n-1) = 2.4v to 4.2v; 0c to +60c vcn - vc(n-1) = 0.1v to 4.7v; 0c to +60c vcn - vc(n-1) = 0.1v to 4.7v; -40c to +85c 3.0 10 15 30 mv cell monitor voltage accuracy v adc absolute cell measurement error (cell measurement error compared with voltage at the cell) vcn - vc(n-1) = 2.4v to 4.2v; 0c to +60c vcn - vc(n-1) = 0.1v to 4.7v; 0c to +60c vcn - vc(n-1) = 0.1v to 4.7v; -40c to +85c -15 -20 -30 15 20 30 mv v batt voltage accuracy v batt v batt - [vbb:vb0] 10 *32*1.8/4095; 0c to +60c -40c to +85c -200 -270 200 270 mv current sense amplifier specifications charge current threshold vccth vcs1-vcs2, ching indicates charge current vcs1 = 26.4v -100 v discharge current threshold vdcth vcs1 -vcs2, dching indicates discharge current; vcs1 = 26.4v 100 v current sense accuracy via1 v ia1 = ([isnsb:isns0] 10 *1.8/4095)/5; ching bit set gain = 5 vcs1 = 26.4v, vcs2 - vcs1 = + 100mv 97 102 107 mv via2 v ia2 = ([isnsb:isns0] 10 *1.8/4095)/5; dching bit set gain = 5 vcs1 = 26.4v, vcs2 - vcs1 = - 100mv -107 -102 -97 mv via3 v ia3 = ([isnsb:isns0] 10 *1.8/4095)/50; ching bit set gain = 50 vcs1 = 26.4v, vcs2 - vcs1 = + 10mv 8.0 10.0 12.0 mv via4 v ia4 = ([isnsb:isns0] 10 *1.8/4095)/50; dching bit set gain = 50 vcs1 = 26.4v, vcs2 - vcs1 = - 10mv -12.0 -10.0 -8.0 mv via5 v ia3 = ([isnsb:isns0] 10 *1.8/4095)/500; ching bit set gain = 500 vcs1 = 26.4v, vcs2 - vcs1 = + 1mv 0c to +60c -40c to +85c 0.5 0.4 1.0 1.5 1.6 mv via6 v ia4 = ([isnsb:isns0] 10 *1.8/4095)/500; dching bit set. gain = 500 vcs1=26.4v, vcs2 - vcs1 = - 1mv 0c to +60c -40c to +85c -1.5 -1.6 -1.0 -0.5 -0.4 mv electrical specifications v dd = 26.4v, t a = -40c to +85c, unless otherwise specified. boldface specification limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test condition min ( note 7 )typ max ( note 7 )units
isl94203 11 fn7626.4 august 17, 2015 submit document feedback overcurrent/short circuit protection specifications discharge overcurrent detection threshold v ocd v ocd = 4mv [ocd2:0] = 0,0,0 2.6 4 5.4 mv v ocd = 8mv [ocd2:0] = 0,0,1 6.4 8 9.6 mv v ocd = 16mv [ocd2:0] = 0,1,0 12.8 16 19.2 mv v ocd = 24mv [ocd2:0] = 0,1,1 20 25 30 mv v ocd = 32mv [ocd2:0] = 1,0,0 (default) 26.4 33 39.6 mv v ocd = 48mv [ocd2:0] = 1,0,1 42.5 50 57.5 mv v ocd = 64mv [ocd2:0] = 1,1,0 60.3 67 73.7 mv v ocd = 96mv [ocd2:0] = 1,1,1 90 100 110 mv discharge overcurrent detection time t ocdt [ocdta:ocdt0] = 0a0h (160ms) (default) range: 0ms to 1023ms 1ms/step 0s to 1023s; 1s/step 160 ms short circuit detection threshold v scd v scd = 16mv [scd2:0] = 0,0,0 10.4 16 21.6 mv v scd = 24mv [scd2:0] = 0,0,1 18 24 30 mv v scd = 32mv [scd2:0] = 0,1,0 26 33 40 mv v scd = 48mv [scd2:0] = 0,1,1 42 49 56 mv v scd = 64mv [scd2:0] = 1,0,0 60 67 74 mv v scd = 96mv [scd2:0] = 1,0,1 (default) 90 100 110 mv v scd = 128mv [scd2:0] = 1,1,0 127 134 141 mv v scd = 256mv [scd2:0] = 1,1,1 249 262 275 mv short circuit current detection time t sct [scta:sct0] = 0c8h (200s) (default) range: 0s to 1023s; 1s/step 0ms to 1023ms 1ms/step 200 s charge overcurrent detection threshold v occ v occ = 1mv [occ2:0] = 0,0,0 0.2 1 2.1 mv v occ = 2mv [occ2:0] = 0,0,1 0.7 2 3.3 mv v occ = 4mv [occ2:0] = 0,1,0 2.8 4 5.2 mv v occ = 6mv [occ2:0] = 0,1,1 4.5 6 7.5 mv v occ = 8mv [occ2:0] = 1,0,0 (default) 6.6 8 9.8 mv v occ = 12mv [occ2:0] = 1,0,1 9.6 12 14.4 mv v occ = 16mv [occ2:0] = 1,1,0 14.5 17 19.6 mv v occ = 24mv [occ2:0] = 1,1,1 22.5 25 27.5 mv overcurrent charge detection time t occt [occta:occt0] = 0a0h (160ms) (default) range: 0ms to 1023ms 1ms/step 0s to 1023s; 1s per step 160 ms charge monitor input threshold (falling edge) v chmon ccmon bit = ?1?; cmon_en bit = ?1? 8.2 8.9 9.8 v load monitor input threshold (rising edge) v ldmon clmon bit = ?1?; lmon_en bit = ?1? 0.45 0.6 0.75 v load monitor output current i ldmon clmon bit = ?1?; lmon_en bit = ?1? 62 a electrical specifications v dd = 26.4v, t a = -40c to +85c, unless otherwise specified. boldface specification limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test condition min ( note 7 )typ max ( note 7 )units
isl94203 12 fn7626.4 august 17, 2015 submit document feedback voltage protection specifications overvoltage lockout threshold (rising edge - any cell) [vcn-vc(n-1)] v ovlo [ovlob:ovlo0] = 0e80h (4.35v) (default) range: 12-bit value (0v to 4.8v) 4.35 v overvoltage lockout recovery threshold - all cells v ovlor falling edge v ovr v undervoltage lockout threshold (falling edge - any cell) [vcn-vc(n-1)] v uvlo [uvlob:uvlo0] = 0600h (1.8v) (default) range: 12-bit value (0v to 4.8v) 1.8 v undervoltage lockout recovery threshold - all cells v uvlor rising edge v uvr v overvoltage lockout detection time t ovlo normal operating mode 5 consutive samples over the limit (min = 160ms, max = 192ms) 176 ms undervoltage lockout detection time t uvlo normal operating mode 5 consecutive samples under the limit (min = 160ms, max = 192ms) 176 ms overvoltage threshold (rising edge - any cell) [vcn-vc(n-1)] v ov [ovlb:ovl0] = 0e2ah (4.25v) (default) range: 12-bit value (0v to 4.8v) 4.25 v overvoltage recovery voltage (falling edge - all cells) [vcn-vc(n-1)] v ovr [ovrb:ovr0] = 0dd5h (4.15v) (default) range: 12-bit value (0v to 4.8v) 4.15 v overvoltage detection/release time t ovt [ovta:ovt0] = 201h (1s) (default) range: 0ms to 1023ms; 1ms/step 0s to 1023s; 1s/step 1s undervoltage threshold (falling edge - any cell) [vcn-vc(n-1)] v uv [uvlb:uvl0] = 0900h (2.7v) (default) range: 12-bit value (0v to 4.8v) 2.7 v undervoltage recovery voltage (rising edge - all cells) [vcn-vc(n-1)] v uvr [uvrb:uvr0] = 0a00h (3.0v) (default) range: 12-bit value (0v to 4.8v) 3.0 v undervoltage detection time t uvt [uvta:uvt0] = 201h (1s) (default) range: 0ms to 1023ms; 1ms/step 0s to 1023s; 1s/step 1s undervoltage release time t uvtr [uvta:uvt0] = 201h (1s) + 2s (default) range: (0ms to 1023ms) + 2s; 1ms/step (0s to 1023s) + 2s; 1s/step 3s sleep voltage threshold (falling edge - any cell) [vcn-vc(n-1)] v sll [sllb:sll0] = 06aah (2.0v) (default) range: 12-bit value (0v to 4.8v) 2.0 v sleep detection time t slt [slta:slt0] = 201h (1s) (default) range: 0ms to 1023ms; 1ms/step 0s to 1023s; 1s/step 1s low voltage charge threshold (falling edge - any cell) [vcn-vc(n-1)] v lvch [lvchb:lvch0] = 07aah (2.3v) (default) range: 12-bit value (0v to 4.8v) pre-charge if any cell is below this voltage 2.3 v low voltage charge threshold hysteresis v lvchh 117 mv electrical specifications v dd = 26.4v, t a = -40c to +85c, unless otherwise specified. boldface specification limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test condition min ( note 7 )typ max ( note 7 )units
isl94203 13 fn7626.4 august 17, 2015 submit document feedback end-of-charge threshold (rising edge - any cell) [vcn-vc(n-1)] v eoc [eocsb:eocs0] = 0e00h (4.2v) (default) range: 12-bit value (0v to 4.8v) 4.2 v end-of-charge threshold hysteresis v eoch 117 mv sleep mode timer t smt [mod7:mod0] = 0dh (off) (default) range: 0s to 255 minutes 90 min watchdog timer t wdt [wdt4:wdt0] = 1fh (31s) (default) range: 0s to 31s 31 s temperature protection specifications internal temperature shutdown threshold t itsd [iotsb:iots0] = 02d8h 115 c internal temperature recovery t itrcv [iotrb:iotr0] = 027dh 95 c external temperature output voltage v tempo voltage output at tempo pin (during temperature scan); i tempo = 1ma 2.3 2.45 2.6 v external temperature limit threshold (hot) - xt1 or xt2 charge, discharge, cell balance (see figure 3 ) t xth xtn hot threshold. voltage at v tempi , xt1 or xt2 = 04b6h tgain = 0 ~+55c; thermistor = 3.535k detected by cot, dot, cbot bits = 1 0.265 v external temperature recovery threshold (hot) - xt1 or xt2 charge, discharge, cell balance (see figure 3 ) t xthr xtn hot recovery voltage at v tempi xt1 or xt2 = 053eh tgain = 0 (~+50c; thermistor = 4.161k) detected by cot, dot, cbot bits = 0 0.295 v external temperature limit threshold (cold) - xt1 or xt2 charge, discharge, cell balance (see figure 3 ) t xtc xtn cold threshold. voltage at v tempi xt1 or xt2 = 0bf2h tgain = 0 (~ -10c; thermistor = 42.5k) detected by cut, dut, cbut bits 0.672 v external temperature recovery threshold (cold) - xt1 or xt2 charge, discharge, cell balance (see figure 3 ) t xtch xtn cold recovery voltage at v tempi . xt1 or xt2 = 0a93h tgain = 0 (~5c; thermistor = 22.02k) detected by cut, dut, cbut bits 0.595 v cell balance specifications cell balance fet gate drive current vc1 to vc5 (current out of pin) 15 25 35 a vc6 to vc8 (current into pin) 15 25 35 a cell balance max voltage threshold (rising edge - any cell) [vcmax] v cbmx [cbvub:cbvu0] = 0e00h (4.2v) (default) range: 12-bit value (0v to 4.8v) 4.2 v cell balance max threshold hysteresis v cbmxh 117 mv cell balance min voltage threshold (falling edge - any cell) [vcmin] v cbmn [cbvlb:cbvl0] = 0a00h (3.0v) (default) range: 12-bit value (0v to 4.8v) 3.0 v cell balance min threshold hysteresis v cbmnh 117 mv electrical specifications v dd = 26.4v, t a = -40c to +85c, unless otherwise specified. boldface specification limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test condition min ( note 7 )typ max ( note 7 )units
isl94203 14 fn7626.4 august 17, 2015 submit document feedback cell balance max voltage delta threshold (rising edge - any cell) [vcn-vc(n-1)] v cbdu [cbdub:cbd0] = 06aah (2.0v) (default) range: 12-bit value (0v to 4.8v) 2.0 v cell balance max voltage delta threshold hysteresis v cbduh 117 mv wake up specifications device chmon pin voltage threshold (wake on charge) (rising edge) v wkup1 chmon pin rising edge device wakes up and sets sleep flag low 7.0 8.0 9.0 v device ldmon pin voltage threshold (wake on load) (falling edge) v wkup2 ldmon pin falling edge device wakes up and sets sleep flag low. 0.15 0.4 0.7 v open wire specifications open wire current i ow 1.0 ma open wire detection threshold v ow1 vcn-vc(n-1); vcn is open. (n = 2, 3, 4, 5, 6, 7, 8). open wire detection active on the vcn input. -0.3 v v ow2 vc1-vc0; vc1 is open. open wire detection active on the vc1 input. 0.4 v v ow3 vc0-vss; vc0 is open. open wire detection active on the vc0 input. 1.25 v fet control specifications dfet gate voltage v dfet1 (on) 100a load; v dd = 36v 47 52 57 v v dfet2 (on) 100a load; v dd = 6v 8 9 10 v v dfet3 (off) 0 v cfet gate voltage (on) v cfet1 (on) 100a load; v dd = 36v 47 52 57 v v cfet2 (on) 100a load; v dd = 6v 8 9 10 v v cfet3 (off) v dd v pcfet gate voltage (on) v pfet1 (on) 100a load; v dd = 36v 47 52 57 v v pfet2 (on) 100a load; v dd = 6v 8 9 10 v v pfet3 (off) v dd v fet turn-off current (dfet) i df(off) 14 15 16 ma fet turn-off current (cfet) i cf(off) 9 13 17 ma fet turn-off current (pcfet) i pf(off) 9 13 17 ma fetsoff rising edge threshold v fo(ih) fetsoff rising edge threshold. turn off fets 1.8 v fetsoff falling edge threshold v fo(il) fetsoff falling edge threshold. turn on fets 1.2 v serial interface characteristics ( note 8 ) input buffer low voltage (scl, sda) v il voltage relative to v ss of the device -0.3 v rgo x 0.3 v input buffer high voltage (scl, sdai, sdao) v ih voltage relative to v ss of the device v rgo x 0.7 v rgo +0. 1 v output buffer low voltage (sda) v ol i ol = 1ma 0.4 v sda and scl input buffer hysteresis i 2 chyst sleep bit = 0 0.05 x v rgo v electrical specifications v dd = 26.4v, t a = -40c to +85c, unless otherwise specified. boldface specification limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test condition min ( note 7 )typ max ( note 7 )units
isl94203 15 fn7626.4 august 17, 2015 submit document feedback scl clock frequency f scl 400 khz pulse width suppression time at sda and scl inputs t in any pulse narrower than the max spec is suppressed. 50 ns scl falling edge to sda output data valid t aa from scl falling crossing v ih (min), until sda exits the v il (max) to v ih (min) window 0.9 s time the bus must be free before start of new transmission t buf sda crossing v ih (min) during a stop condition to sda crossing v ih (min) during the following start condition 1.3 s clock low time t low measured at the v il (max) crossing 1.3 s clock high time t high measured at the v ih (min) crossing 0.6 s start condition setup time t su:sta scl rising edge to sda falling edge, both crossing the v ih (min) level 0.6 s start condition hold time t hd:sta from sda falling edge crossing v il (max) to scl falling edge crossing v ih (min) 0.6 s input data setup time t su:dat from sda exiting the v il (max) to v ih (min) window to scl rising edge crossing v il (min) 100 ns input data hold time t hd:dat from scl falling edge crossing v ih (min) to sda entering the v il (max) to v ih (min) window 00.9 s stop condition setup time t su:sto from scl rising edge crossing v ih (min) to sda rising edge crossing v il (max) 0.6 s stop condition hold time t hd:sto from sda rising edge to scl falling edge. both crossing v ih (min) 0.6 s data output hold time t dh from scl falling edge crossing v il (max) until sda enters the v il (max) to v ih (min) window 0 ns sda and scl rise time t r from v il (max) to v ih (min) 300 ns sda and scl fall time t f from v ih (min) to v il (max) 300 ns sda and scl bus pull-up resistor- off chip r out maximum is determined by t r and t f for c b = 400pf, max is 2k ~ 2.5k for c b = 40pf, max is 15k ? ~ 20k 1 k input leakage (scl, sda) i li - 10 10 a eeprom write cycle time t wr +25c 30 ms notes: 7. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. device min and/or max values are based on temperature limits established by characte rization and are not production tested. 8. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications v dd = 26.4v, t a = -40c to +85c, unless otherwise specified. boldface specification limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test condition min ( note 7 )typ max ( note 7 )units
isl94203 16 fn7626.4 august 17, 2015 submit document feedback symbol table timing diagrams external temperature configuration wake-up timing waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance waveform inputs outputs thermistors: 10k, murata xh103f 10k 10k xt2 pin xt1 pin tempo pin 22k 22k figure 3. external temperature configuration digital temperature voltage reading = xtn * 2 (tgain bit = 0) xtn * 1 (tgain bit = 1) ldmon pin in_sleep bit v wkup2 <1s v wkup1 <1s chmon pin in_sleep bit figure 4. wake-up timing (from sleep) can stay in sleep mode dfet/cfet ~140ms ~50ms enters sleep mode if ldmon or chmon is ?active? when entering sleep mode, the ic wakes up after a short delay. can stay in sleep mode can stay in sleep mode can stay in sleep mode
isl94203 17 fn7626.4 august 17, 2015 submit document feedback change in fet control chmon pin v wkup1 figure 5. power-up timing (from power up/shutdown) dfet/cfet ~3s ldmon check 256ms turn on fets if no pack faults i 2 c communication ~4ms rgo bit 0 dfet/cfet turn on sda scl bit 0 data bit 1 bit 1 bit 3 bit 2 ack ack 10% 90% t fton 10% 90% t ftoff figure 6. i 2 c fet control timing ~1s ~1s (~500s if both fets off) dfet/cfet turn on ~1s figure 7. fetsoff fet control timing ~1s fetsoff pin v fo(on) v fo(off) fet charge pump ~500s
isl94203 18 fn7626.4 august 17, 2015 submit document feedback automatic temperature scan serial interface timing diagrams bus timing tempo pin delay time = 20s 128ms monitor time = 120s 2.5v cbot, dot, cot bits external over-temperature delay time = 20s fet shutdown or ce ll balance turn of monitor temperature during this time period threshold temperature (if enabled) figure 8. automatic temperature scan over-temp under-temp xtn xt1 xt2 xt1 xt2 1024ms 2048ms see figure 3 for test circuit t su:sto t high t su:sta t hd:sta t hd:dat t su:dat scl t f t low t buf t r t dh t aa sda (input timing) sda (output timing) figure 9. serial interface bus timing
isl94203 19 fn7626.4 august 17, 2015 submit document feedback discharge overcurrent/short-circuit monitor charge overcurrent monitor (assumes no_occr bit is ?0?) v sc v ocd t scd t ocd t scd doc bit dsc bit sd v dsense c register 1 read c register 1 read output 2.5v 1 1 0 0 dfet output isl94203 turns on dfet c is optional ldmon detects load release ldmon detects load release resets doc, scd bit, turns on fet resets doc, scd bit, turns on fet figure 10. discharge/short circuit monitor (cfet bit = 0) v dd +15v v ldmon load releases during this time ldmon pin detects 2 ldmon pulses above threshold 3 s 256ms v occ t occ coc bit sd v csense register 1 read output 2.5v 1 0 cfet output isl94203 turns on cfet v dd +15v chmon detects charger release resets doc, scd bit, turns on fet (cfet bit = 0) figure 11. charge overcurrent monitor v chmon charger releases chmon pin detects 2 chmon pulses below threshold
isl94203 20 fn7626.4 august 17, 2015 submit document feedback functional description this ic is intended to be a stand-alone battery pack monitor, so it provides monitor and protection functions without using an external microcontroller. the part locates the power control fets on the high side with a built-in charge pump for driving n-channel fets. the current sense resistor is also on the high side. power is minimized in all areas, with parts of the circuit powered down a majority of the time, to extend battery life. at the same time, the rgo output stays on, so that any connected microcontroller can remain on most of the time. the isl94203 includes: ? input level shifter to enable monitoring of battery stack voltages ? 14-bit adc converter, with voltage readings trimmed and saved as 12-bit results ? 1.8v voltage reference (0.8% accurate) ? 2.5v regulator, with the volt age maintained during sleep ? automatic scan of the cell voltages; overvoltage, undervoltage and sleep voltage monitoring ? selectable overcurrent detection settings - 8 discharge overcurrent thresholds - 8 charge overcurrent thresholds - 8 short circuit thresholds - 12-bit programmable discharge overcurrent delay time - 12-bit programmable charge overcurrent delay time - 12-bit programmable sh ort-circuit delay time ? current sense monitor with gain that provides the ability to read the current sense voltage ? second external temperature sens or for use in monitoring the pack or power fet temperatures ? eeprom for storing operating parameters and a user area for general purpose pack information battery connections power path figure 12 shows the main power path connections for a single charge/discharge path. figure 13 shows the connection for separate charge/discharge paths. these figures show schottky diodes on the vdd pin. these are to maintain the voltage on the vdd pin during high current conditions or when the charge fe t is off. these are not needed if v dd can be maintained within 0.5v of v batt . the chmon pin connects to the pack pin that receives the charge and the ldmon pin connects to the pack pin that drives the load. for the single path application, these pins can tie together. pack configuration a register in eeprom (cells) identifies the number of cells that are supposed to be present, so the isl94203 only scans these cells. this register is also used for the cell balance operation. the register contents are a 1:1 representation of the cells connected to the pack. for example, in a 6 cell pack, the value in cells is ?11100111? (cfh), which indicates that cells 1, 2, 3, 6, 7 and 8 are connected. also see figure 14 on page 21 . vbatt cs2 pack+ cfet ldmon n-channel fets chmon pcfet 1k 47nf bat+ 1k 47nf figure 12. single path fet drive/power supply detail chg+ dischg+ 100 470nf cs1 vc8 vc7 vdd dfet vbatt cs2 cfet ldmon n-channel fets chmon pcfet 1k 47nf bat+ 1k 47nf figure 13. dual path fet drive/power supply detail chg+ dischg+ 100 470nf cs1 vc8 vc7 vdd dfet 3.3m 500 500
isl94203 21 fn7626.4 august 17, 2015 submit document feedback battery cell connections suggested connections for pack configurations varying from 3 cells to 8 cells are shown in figure 14 . operating modes power-up operation when the isl94203 first connects to the battery pack, it is unknown which pins connect first or in what order. when the vdd and vss pins connect, the device enters the power-down state. it remains in this state until a charger is connected. the device will also power up if the chmon pin is connected to the vdd pin through an outside resistor to si mplify the pcb manufacture. it is possible that the pack powers up automatically when the battery stack is connected due to momentary conduction through the power fet g-s and g-d capacitors. once the charger connects (or chmon connects), the internal power supply turns on. this powers up all internal supplies and starts the state machine. if so me cells are not connected, the state machine recognizes this, either through the open wire test (see ? typical operating conditions ? on page 24 ) or because the monitored cell voltage reads zero, when the ?cells? register indicates that there should be a voltage at that pin. if the cell voltages do not read correctly, then the isl94203 remains in the por loop until conditions are valid for power-up (it is for this reason that the factory default for the device is 3 cells. when manufacturing the application board, cells 1, 2 and 8 must be connected to power up. if other cells are connected it is ok, but for the other cells to be monitored, the cells register needs to be changed). note: multiple c ells can be connected in parallel 6 cells 3 cells 4 cells vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss 8 cells cb7 cb6 cb5 cb4 cb3 cb2 cb1 figure 14. battery connection options vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 5 cells 7 cells vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0
isl94203 22 fn7626.4 august 17, 2015 submit document feedback if the inputs all read good duri ng this sequence, then the state machine enters the normal monitor state. in the normal state, if all cell voltages read good an d there are no overcurrent or temperature issues and there is no load, the fets turn on. to determine if there is a load, the device does a load check. this operation waits for about three seconds and then must see no load for two successive load monitor cycles (256ms apart). during the por operation, the ram registers are all reset to default conditions from values saved in the eeprom. when the cell voltages drop, th e isl94203 remains on if the vdd voltage remains above 1v and the vrgo voltage is above 2.25v. this is to maintain operation of the device in the event of a short drop in cell voltage due to a pack short circuit condition. in the event of a longer battery stack voltage drop, then the device will return to a power-down condition if v dd drops below a por threshold of about 3.5v when v rgo is below 2.25v (see figures 15 and 16 ). power on reset fets off, no current scan. power-down state charger connect scan only voltage s, temp, load all voltages ok temp ok ? do a voltage scan. ? only look at cells that are specified in the cell reg. ? if all cell voltages and temps are ok, do a load test. ? if there are any errors, keep scanning voltages, temperatures and load at normal scan rates. normal operating mode figure 15. power on reset state machine no load v rgo < 1.2v (any cell < v uvlo for 160ms and uvlopd = 1) or or pdwn bit set battery stack connect and v dd > v por 6v vdd last cell connected por scan rgo por (reset 2.25v uv uvr dfet figure 16. power-up/power-down/low voltage waveforms por ~3.5v while rgo is above 2.25v, v dd dropping below por does not caus e a power-down powered state chmon registrs) ldmon 3 s
isl94203 23 fn7626.4 august 17, 2015 submit document feedback wake-up circuit when in a sleep mode, the wake-up circuit detects that the output pin is pulled low (as might be the case when a load is attached to the pack and the fets are off) or pulled high (as might be the case when the charger is connected and the fets are off). the wake-up circuit does not draw significant continuous current from the battery. low power states in order to minimize power consumption, most circuits are kept off when not being used and items are sampled when possible. there are five power states in the device (see figure 17 ). normal mode this is the normal monitoring/scan mode. in this mode, the device monitors the current cont inuously and scans the voltages every 32ms. if balancing is called for, then the device activates external balancing components. all necessary circuits are on and unnecessary circuits are off. during the scan, the isl94203 draw s more current as it activates the input level shifter, the adc and data processing. between scans, circuits turn off to minimize power consumption. idle mode if there is no current flowing for 0 to 15 minutes (set in the mod register), then the device enters the idle mode. in this mode, voltage scanning slows to every 256ms per scan. the fets and the ldo remain on. in this mode, the device consumes less current, because there is more time between scans. when the isl94203 detects any ch arge or discharge current, the device exits the idle mode and returns to the normal mode of operation. the device does not automatically enter the idle mode if the cscan bit is set to ?1?, because the microcontroller is in charge of performing the scan an d controlling the operation. setting the idle bit to ?1? forces the device to enter idle mode, regardless of current flow. when a c sets the idle bit, the device remains in idle, regardless of the timer or the current. setting the mode control bits to 0 allows the device to control the mode. doze mode while in idle mode, if there is no current flowing for another 0 to 16 minutes (same value as the idle timer), the device enters the doze mode, where cell voltage sampling occurs every 512ms. the fets and the ldo remain on. in this mode, the device consumes less current than idle mode, because there is more time between scans. when the isl94203 detects any ch arge or discharge current, the device exits doze mode and returns to the normal mode. the device does not automatically enter the idle mode if the cscan bit is set to ?1?, because the microcontroller is in charge of performing the scan an d controlling the operation. setting the doze bit forces the device to enter the doze mode, regardless of the current flow. when a microcontroller sets the doze bit, the device remains in doze mode regardless of the timer or the current. setting the mo de control bits to 0 allows the device to control the mode. note: setting the idle/doze timer to 0 immediately forces the device into the doze mode when there is no current. sleep mode the isl94203 enters the sleep mo de when the voltage on the cells drops below the sleep voltage threshold for a period of time, specified by the sleep delay timer. to prevent the device from entering the sleep mode by a low voltage on the cells, the sleep voltage level (sll) register can be set to 0. the device can also enter the sleep mode from the doze mode, if there has been no detected cu rrent for more than the duration of the sleep mode timer (set in the mod register). in this case, the device remains in doze mode until there has been no current for 0 to 240 minutes (with 16 minute steps). the external microcontroller forc es the isl94203 to enter sleep mode by writing to the sleep bit (register 88h). setting the sleep bit forces the sleep mode, regardless of the current flow. note: if both idle/doze and sleep timers are set to 0, the device immediately goes to sleep. to recover from this condition, apply current to the device or hold the ldmon pin low (or chmon pin high) and write non-zero values to the registers. while in the sleep mode, everything is off except for the 2.5v regulator and the wake up circuits. the device can be waken by ldmon connection to a load or chmon connection to a charger. power-down mode this mode occurs when the voltage on the pack is too low for proper operation. this occurs when: ?v dd is less than the por threshold and rgo < 2.25v. this condition occurs if cells discharge over a long period of time. ?v dd is less than 1v and rgo > 2.25v. this condition can occur during a short circuit with minimum capacity cells. the v dd drops out, but the rgo cap maintains the logic supply. ? when any cell voltage is less than the uvlo threshold for more than about 160ms (and uvlopd = 1). ? if commanded by an external c. recovering out of any low power state brings the isl94203 into the normal operating mode. exceptions there is one exception to the normal sequence of mode management. when the microcontro ller sets the cscan bit, the internal scan stops. this means that the device no longer looks for the conditions required for sl eep. the external microcontroller needs to manage the modes of operation. the lower device in a cascaded stack of isl94203s does not detect current. as such, the device will progress through the power states to sleep regardless of the pack current. an external c needs to set the operating state to idle or doze to prevent the lower device from going to sleep.
isl94203 24 fn7626.4 august 17, 2015 submit document feedback typical operating conditions table 1 shows some typical device operating parameters. cell fail detection the cell fail (cellf) condition indicates that the difference between the highest voltage cell and the lowest voltage cell exceeds a programmed threshold (as specified in the cbdu register). once detected, the cellf condition turns off the cell balance fets and the power fets, but only if the cfet bit = ?0.? setting the cfet bit = ?1? prevents the power fets from turning off during a cellf condition. the microcontroller is then responsible for the power fet control. an eeprom bit, cfpsd, when set to ?1?, enables the psd activation when the isl94203 dete cts a cell fail condition. when cellf = ?1? and cfpsd = ?1?, the power fets and cell balance fets turn off, plus the psd output goes active. the pack designer can use the psd pin output to deactivate the pack by blowing a fuse. the cellf function can be disabled by setting the cbdu value to fffh. in this case, the voltage differential can never exceed the limit. however, disabling the cell fail condition also disables the open wire detection (see ? open wire detection ? on page 25 ). {any cell voltage less than uvlo for 160ms and uvlopd = 1} or rgo < 1.2v or pdwn bit set to 1 power-down state normal operating state power consumption average first power up: voltag e on vdd rises above the por threshold. already powered: a charger wake up signal. power consumption <1a 450a (2ma peaks) idle state no charge or discharge current detected for 1-16 mi n or idle bit is set power consumption average 350a max (2ma peaks) doze state no charge or discharge current detected for 1 to 16 min or doze bit is set power consumption average 300a (2ma peaks) sleep state no charge or discharge current detected for 32 to 256 min or sleep bit is set power consumption average 15a any cell voltage drops below sleep threshold for sleep delay time or sleep bit is set wake up signal (either charger or load) figure 17. isl94203 power states when the device detects any charge or discharge current, operation moves from doze or idle states back to the normal operating state
isl94203 25 fn7626.4 august 17, 2015 submit document feedback open wire detection there is a special open battery wire detection function on this device. the most important reason for an open wire detection is to turn off the power fets if there is an open wire to prevent the cells from being excessively charged or discharged. secondarily, the open wire functi on prevents the operation of cell balancing when there is an open wire. there are two reasons for this. first, if there is an open wire, cell balancing is compromised. second, when the cell balance turns on the external balancing fet and there is an open wire, excessive voltage may appear on the isl94203 vcn input pins. inte rnal clamps and input series resistors prevent damage as a result of short term exposure to higher input voltages. the open wire feature uses built in circuits to force short pulses of current into or out of the input capacitors (see figure 18 ). when there is no open wire, the ba ttery cell itself changes little in response to the open wire test. the open wire operation is disabled by setting a control bit (dowd) to ?1?. when enabled (dowd = ?0?), the isl94203 performs an open wire test when the cellf condition exists and then once every 32 voltage scans as long as the cellf condition remains. a cellf condition is the first indication that there might be an open wire. in operation, the open wire circuit pulls (or pushes) 1ma of current sequentially on each vcn input for a period of time. the open wire on-time is programmable by a value in the owt register. the pulse duration is programmable between 1s and 512ms. the default values for cu rrent and time are 1ma current and 1ms duration. note: in the absence of a battery cell, 1ma input current, along with an external capacitor of 4.7nf, changes the voltage of the input to the open wire threshold of -1.4v (relative to the adjacent cell) within 30s. with the cell present, the voltage will have a negligible change. each input has a comparator that detects if the voltage on an input drops more than 1.4v belo w the voltage of the cell below. exceptions are vc1 and vc0. for vc1, the circuit looks to see if the voltage drops below 1v. for vc0, the circuit looks to see if the voltage exceeds 1.4v. if any comp arator trips, then the device sets an open error flag indicating an open wire failure and disables cell balancing. see figure 19 for sample timing. with the open wire setting of 1ma, input resistors of 1k create a voltage drop of 1v. this voltag e drop, combined with the body diode clamp of the cell balance fet, provides the -1.4v needed to detect an open wire. for this reason and for the increased protection, it is not recommen ded that smaller input series resistors be used. for example, with a 100 input resistor, the voltage across the input resistor drops only 0.1v. this will not allow the input open wire detection hardware to trigger (although the digital detection of open wi re still works, the hardware detection automatically turns off the open wire current). input resistors larger than 1k may be desired to increase the input filtering. this is allowed in the open wire test, by providing an increase in the detection time (by changing the owt value.) however, increasing the input re sistors can significantly affect measurement accuracy. the isl94203 has up to 2a variation in the input measurement current. this amounts to about 2mv measurement error with 1k resist ors (this error has been factory calibrated out). however, 10k resistors can result in up to 20mv measurement errors. to increase the input filtering, the preferred method is to increase the size of the capacitors. note: the open wire test is run only if the device detects the cellf condition and then once every 32 voltage scans while a cellf condition exists. each current source is turned on sequentially. figure 18. open wire detection internal 2.5v supply control logic cell n cell 4 cell 3 cell 2 cell 1 vc0 vc1 vc2 vc3 vc4 vcn
isl94203 26 fn7626.4 august 17, 2015 submit document feedback depending on the selection of the input filter components, the internal open wire comparators may not detect an open wire condition. this might happen if the input resistor is small. in this case, the body diode of the cell balance fet may clamp the input before it reaches the open wire detection threshold. to overcome this limitation and provide a redu ndant open wire detection, at the end of the open wire scan, all input voltages are converted to digital values. if any digital value equals 0v (minimum) or 4.8v (maximum), the device sets an open error flag indicating an open wire failure. when an open wire condition occurs and the ?open wire power shut down? bit (owpsd) is equal to ?0?, the isl94203 turns off all power fets and the cell balance fets, but does not set the psd output. while in this condit ion, the device continues to operate normally in all other ways (i.e. the cells are scanned and the current monitored. as time passes, the device drops into lower power modes). when an open wire condition oc curs and owpsd = ?1?, the open flag is set, the isl94203 turns off all power fets and the cell balance fets and the isl94203 sets the psd output port active. the device can automatically recover from an open wire condition, because the open wire test is still functional, unless the owpsd bit equals 1 and the psd pin blows a fuse in the pack. if the open wire test finds that the open wire has been cleared, then open bit is reset and other tests determine whether conditions allow the power fets to turn back on. the open wire test hardware has tw o limitations. fi rst, it depends on the cellf indicator. if th e cell balance maximum voltage delta (cbdu) value is set to high (fffh for example), then the device may never detect a cellf condition. the second limitation is that the open wire test does not happen immediately. first, a scan must detect a cellf condit ion. cellf detection happens in a maximum of 32ms (normal mode) or in a maximum of 256ms (doze mode). once cellf is detected, the open wire test occurs on the next scan, 32ms to 256ms later. current and voltage monitoring there are two main automatic processes in the isl94203. the first are the current monitor and overcurrent shutdown circuits. the second are the voltage, temp erature and current analog to digital scan circuits. notes: 9. voltage drop = 1ma * 1k = 1v 10. voltage = v f of cb5 balance fet body diode + (1ma * 1k ) 11. owpsd bit = 0 12. this time is 8s in idle and 16s in doze 13. this 32ms scan rate increases to 256ms in idle and 512ms in doze figure 19. open wire test timing vc max - vc min pack cell imbalance pack vc5 open wire cellf threshold pack open wire cleared ~160ms (default) open wire scan vc8 ow test vc7 ow test vc6 ow test vc5 ow test vc4 ow test vc3 ow test vc2 ow test vc1 ow test voltage scan t ow open bit ~1ms vc6 vc5 vc4 1v ~1.7v no open wire scans voltage scan reports that vc5 = 0v and vc6 = 4.8v cellf bit default = 20ms 1s 32ms cbal fets turn off ( note 9 ) ( note 10 ) ( note 12 ) ( note 13 )
isl94203 27 fn7626.4 august 17, 2015 submit document feedback current monitor the current monitor is an analog detection circuit that tracks the charge and discharge current and current direction. the current monitor circuit is on all the time, except in sleep and power down modes. the current monitor compares the voltage across the sense resistor to several different thresholds. these are short circuit (discharge), overcurrent (dischar ge) and overcurrent (charge). if the measured voltage exceeds the specified limit, for a specified duration of time, the isl94203 acts to protect the system, as described in the following. the current monitor also tracks th e direction of the current. this is a low level detection and indicates the presence of a charge or discharge current. if either condition is detected, the isl94203 sets an appropriate flag. current sense the current sense element is on the high-side of the battery pack. the current sense circuit has a gain x5, x50 or x500. the sense amplifier allows a very wide range of currents to be monitored. the gain settings allow a sense resistor in the range of 0.3m to 5m . a diagram of the current sense circuit is shown in figure 20 . there are two parts of the current sense circuit. the first part is a digital current monitor circuit. this circuit allows the current to be tracked by an external microcon troller or computer. the current sense amplifier gain in this current measurement is set by the [cg1:cg0] bits. the 14-bit offset adjusted adc result of the conversion of the voltage across the current sense resistor is saved to ram, as well is a 12-bit value that is used for threshold comparisons. the offset adjustment is based on a ?factory calibration? value saved in eeprom. the digital readouts cover the input voltage ranges shown in table 2 . the second part is the analog current direction, overcurrent and short circuit detect mechanisms. this circuit is on all the time. during the operation of the overcurrent detection circuit, the sense amplifier gain is automatically controlled. table 2. maximum current measurement range gain setting voltage range (mv) current range (r sense = 1m ) 5x -250 to 250 -250a to 250a 50x -25 to 25 -25a to 25a 500x -2.5 to 2.5 -2.5a to 2.5a 4 + - overcurrent charge detect r sense figure 20. block diagram for overcurrent detect and current monitoring + - cs1 cs2 coc [occ2:occ0] overcurrent discharge detect programmable thresholds doc [ocd2:ocd0] short circuit discharge detect programmable thresholds dsc [dsc2:dsc0] ching dching cg1:0 500 5k 50k 250k 250k 14-bit mux programmable thresholds gain select ao2:0 = 9h note: agc sets gain during overcurrent monitoring. cg bits select gain when adc measures current. voltage scan agc programmable detection time [occtb:occ0] [ocdtb:ocdt0] [sctb:sct0] adc 12 + ram register 12-bit pack current programmable detection time programmable detection time address: [8fh:8eh] ram register 14-bit 14-bit adc output value value ao3:ao0 digital cal eeprom voltage select bits address: [abh:aah] direction current detect + 2ms filter polarity control
isl94203 28 fn7626.4 august 17, 2015 submit document feedback for current direction detection, there is a 2ms digital delay for getting into or out of either direction condition. this means that charge current detection circuit needs to detect an uninterrupted flow of current out of the pack for more than 2ms to indicate a discharge condition. then, the current detector needs to identify that there is a charge current or no current for a continuous 2ms to remove the discharge condition. the overvoltage and short circ uit detection thresholds are programmable using values in the eeprom. the discharge overcurrent thresholds are shown in table 3 . the charge overcurrent thresholds are shown in table 4 . the discharge short circuit thresholds are shown in table 5 . the charge and discharge overcurrent conditions and the discharge short circuit condition need to be continuous for a period of time before an overcu rrent condition is detected. these times are set by individual 12-bit timers. the timers consist of a 10-bit timer value and a 2-bit scale value (see table 6 ). overcurrent and short-circuit detection the isl94203 continually monitors current by mirroring the current across a current sense resistor (between the cs1 and cs2 pins) to a resistor to ground. ? a discharge overcurrent condition exists when the voltage across the external sense resistor exceeds the discharge overcurrent threshold, set by the discharge overcurrent threshold bits [ocd2:ocd0], for an overcurrent time delay, set by the discharge overcurrent time out bits [ocdtb:ocdt0]. this condition sets the doc bit high. the ld_prsnt bit is also set high at this time. if the cfet bit is 0, then the power fets turn off automatically. if the cfet bit is 1, then the external c must control the power fets. ? a charge overcurrent condition exists when the voltage across the external sense resistor ex ceeds the charge overcurrent threshold, set by the charge overcurrent threshold bits [occ2:occ0], for an overcurrent time delay, set by the discharge overcurrent time out bits [occtb:occt0]. this condition sets the coc bit high. the ch_prsnt bit is also set high at this time. if the cfet bit is 0, then the power fets turn off automatically. if the cfet bit is 1, then the external c must control the power fets. ? a discharge short circuit condition exists when the voltage across the external sense resistor exceeds the discharge short circuit threshold, set by the discharge short circuit threshold bits [scd2:scd0], for an overcurrent time delay, set by the discharge short circuit time out bits [scdtb:scdt0]. this condition sets the dsc bit high. the ld_prsnt bit is also set high at this time. the power fets turn off automatically in a short circuit condition, regardle ss of the condition of the cfet bit. table 3. discharge overcurrent threshold voltages ocd setting threshold (mv) equivalent current (a) 0.3m 0.5m 1m 2m 5m 000 4 13.3 8 4 2 0.8 001 8 26.6 16 8 4 1.6 010 16 53.3 32 16 8 3.2 011 24 80 48 24 12 4.8 100 32 106.7 64 32 16 6.4 101 48 ( note 14 )96 48 249.6 110 64 ( note 14 )( note 14 ) 64 32 12.8 111 96 ( note 14 )( note 14 )( note 14 ) 48 19.2 note: 14. these selections may not be reasonable due to sense resistor power dissipation. table 4. charge overcurrent threshold voltages occ setting threshold (mv) equivalent current (a) 0.3m 0.5m 1m 2m 5m 000 1 3.3 2 1 0.5 0.2 001 2 6.7 4 2 1 0.4 010 4 13.3 8 4 2 0.8 011 6 20 12 6 3 1.2 100 8 26.6 16 8 4 1.6 101 12 40 24 12 6 2.4 110 16 53.3 32 16 8 3.2 111 24 80 48 24 12 4.8 table 5. discharge short circuit current threshold voltages dsc setting threshold (mv) equivalent current (a) 0.3m 0.5m 1m 2m 5m 000 16 53.3 32 16 8 3.2 001 24 80 48 24 12 4.8 010 32 106.7 64 32 16 6.4 011 48 160 96 48 24 9.6 100 64 213.3 128 64 32 12.8 101 96 ( note 15 ) 192 96 48 19.2 110 128 ( note 15 )( note 15 ) 128 64 25.6 111 256 ( note 15 )( note 15 ) note 128 51.2 note: 15. these selections may not be reason able due to sense resistor power dissipation. assumes short circuit fet turn off in 10ms or less. table 6. charge/discharge overcurrent/short circuit delay times [occtb:a] [ocdtb:a] [sctb:a] scale value [occt9:0] [ocdt9:0] [sct9:0] delay (10-bit value) 00 0 to 1024s 01 0 to 1024ms 10 0 to 1024s 11 0 to 1024 minutes table 5. discharge short circuit current threshold voltages (continued) dsc setting threshold (mv) equivalent current (a) 0.3m 0.5m 1m 2m 5m
isl94203 29 fn7626.4 august 17, 2015 submit document feedback overcurrent and short-circuit response (discharge) once the isl94203 enters the disc harge overcurrent protection or short-circuit protection mode, the isl94203 begins a load monitor state. in the load monitor state, the isl94203 waits three seconds and then periodically checks th e load by turning on the ldmon output for 0 to 15ms every 256m s. program the pulse duration with the [lpw3:lpw0] bits in eeprom. when turned on, the recovery circuit outputs a small current (~60 a) to flow from the device and into the load. with a load present, the voltage on the ldmon pin is low and the ld_prsnt bit remains set to ?1?. when the lo ad rises to a sufficiently high resistance, the voltage on the ldmon pin rises above the ldmon threshold and the ld_prsnt bit is reset. when the load has been released for a sufficiently long peri od of time (two successive load sample periods) the isl94203 reco gnizes that the conditions are ok and resets the doc or dsc bits. if the cfet bit is 0, then the de vice automatically re-enables the power fets by setting the dfet and cfet (or pcfet) bits to ?1? (assuming all other conditions are within normal ranges). if the cfet bit is 1, then the c must turn on the power fets. an external microcontroller ca n override the automatic load monitoring of the device. it does this by taking control of the load monitor circuit (set the clmon bit = ?1?) and periodically pulsing the lmon_en bit. when the microcontroller detects that ld_prsnt= ?0?, the c sets the clr_lerr bit to ?1? (to clear the error condition and reset the doc or dsc bit) and sets the dfet and cfet (or pcfet) bits to ?1? to turn on the power fets. overcurrent response (charge) once the isl94203 enters the charge overcurrent protection mode, the isl94203 begins a charger monitor state. in the charger monitor state, the isl94203 periodically checks the charger connection by turning on the chmon output for 0ms to 15ms every 256ms. program the use duration with the [cpw3:cp0] bits in eeprom. when turned on, the recovery circuit checks the voltage on the chmon pin. with a charger presen t, the voltage on the chmon pin is high (>9v) and the ch_prsnt bi t remains set to ?1?. when the charger connection is removed, the voltage on the chmon pin falls below the chmon threshold and the ch_prsnt bit is reset. when the charger has been released for a sufficiently long period of time (two successive sample periods) the isl94203 recognizes that the conditions are ok and clears the coc bit. if the cfet bit is 0, the device automatically re-enables the power fets by setting the dfet and cfet (or pcfet) bits to ?1? (assuming all other conditions are within normal ranges). if the cfet bit is 1, then the c must turn on the power fets. an external microcontroller can override the automatic charger monitoring of the device. it does this by taking control of the load monitor circuit (set the ccmon bit = ?1?) and periodically pulsing the cmon_en bit. when the microcontroller detects that ch_prsnt = ?0?, the c sets the clr_cerr bit to ?1? (to clear the error condition and reset the coc bit) and sets the dfet and cfet (or pcfet) bits to ?1? to turn on the power fets. sense coc bit overcurrent i occ normal operation mode normal operation mode notes: 16. when cfet = ?1?, coc bit is rese t when the clr_cerr is set to ?1?. 17. when cfet = ?0?, coc is reset by the isl94203 when the condition is released figure 21. charge overcurrent protection mode - event diagram protection mode cfet coc bit (cfet = 0) (cfet = 1) t occt chmon pin v chmon charger still charger removed sample rate set by isl94203 when cfet = 0 cmon_en sample rate set by microcontroller when cfet = 1 and ccmon = 1 (from c) connected current ( note 16 ) ( note 17 )
isl94203 30 fn7626.4 august 17, 2015 submit document feedback microcontroller overcurrent fet control protection if any of the microcontroller ov erride bits (cscan, cfet, clmon, ccmon or cbal) are set to ?1? and the microcontroller does not send a valid slave byte to the isl94203 within the watchdog time out pe riod, then the microcontroller control bits are all reset, the device turns off the power fets and the balance fets and the int output provides a 1s pulse one time per second. notes: 18. when cfet = ?1?, cfet, dfet and pcfet are controlled by external c. when cfet = ?0?, cfet, dfet and pcfet ar e controlled automatically by the isl94203. 19. when cfet = ?1?, doc and dsc bits ar e reset by setting the clr_lerr bit. when cfet = ?0?, doc and dsc are reset by the isl94203 when the condition is released. 20. pcfet turns on if any cell voltage is less than lvchg threshold. otherwise cfet turns on. 21. dfet does not turn on if any cell is less than the uv threshold, unless the dfoduv bit is set. dfet v ss o.c. protection v ocd normal operation mode v ocd normal battery v dsc v dsc normal short t sc ldmon pin lmon_en v ldmon t ocdt doc ld_prsnt load not released load released (external control) doc dsc (stand alone) v cs (from c) cfet pcfet voltage sleep note 18 note 18 note 18 note 19 note 19 note 20 note 20 note 20 note 20 note 21 note 21 figure 22. discharge overcurrent protection mode - event diagram no current for 2x idle/mo de mode time + sleep mode time sample rate set by c when cfet = 0 sample rate is set by c. when cfet = 1 and clmon = 1 3 s 3 s
isl94203 31 fn7626.4 august 17, 2015 submit document feedback voltage, temperature and current scan the voltage scan consists of the monitoring of the digital representation of the current, ce ll voltages, temperatures, pack voltage and regulator voltage. this scan occurs once every 32ms, 256ms or 512ms (depending on the mode of operation, see figure 23 ). the temperature, pack voltage and regulator voltage are scanned only every 4th scan. the open wire is scanned every 32nd scan as long as the cellf condition exists. after each measurement scan, the isl94203 performs an offset adjustment and stores the values in ram. after the values are stored, the state machine execut es compare operations that determine if the pack is op erating within limits. see figure 23 for details on the scan sequence. during manufacture, intersil prov ides calibration values in the eeprom for each cell voltage reading. when there is a new conversion for a particular voltag e, the calibration is applied to the conversion. notes: 22. the open wire test performed every 32 voltage scans, if cellf = 1, just prior to the scan. 23. fets turn off immediately if there is an error, but they do not turn on until the end of the voltage scan (at ?fet update? i f everything else is ok). an exception to this is when a device wakes up when connected to a load. in this case, the fets turn on immediately on wake-up, th en a scan begins. 24. the voltage scan can be turned off by an external microcontroller by setting the cscan bit. this bit is monitored by the wa tchdog timer, so if an external microcontroller stops communicating with the isl94203 for more than the wdt period, this bit is automatically reset an d the scan resumes. mux sel settling time adc convert current/voltage monitor (every cycle) cell1 cell2 cell3 cell8 isl94203 cell voltage monitoring 32ms 256ms isl94203 pack voltage monitoring cell1 cell2 32ms 256ms mux sel settling time adc convert isl94203 temperature monitoring xt1 xt2 current/voltage/temperature monitor (every 4th cycle) current select/settling time isl94203 current monitoring offsets/cb calculations/open wire detect open wire ~100s ~500s v batt /16 ov/uv/uvlo detect/fet update/add offsets/cb calculations/open wire detect ov/uv/uvlo detect/fet update/add temperature calculations it rgo/2 512ms 512ms low power state low power adc convert mux sel settling time adc convert current turn on adc current cell1 cell1 open wire cell7 1ms 1ms ~50s figure 23. cell voltage, curr ent, temperature scanning int_scan bit int_scan bit ~1.3 ms ~1.7 ms
isl94203 32 fn7626.4 august 17, 2015 submit document feedback cell voltage monitoring the circuit that monitors the input cell voltage multiples the cell voltage by 3/8. the adc converts this voltage to a digital value, using a 1.8v internal reference. the adc produces a calibrated 14-bit value, but only 12 bits are stored in the cell registers (see figure 24 .) in manufacturing, each cell voltag e is calibrated at 3.6v per cell and at +25c. this calibrated value is used for all subsequent voltage threshold comparisons. the isl94203 has two different overvoltage and undervoltage level comparisons, ovlo/uvlo and ov/uv. while both use the adc converter output values and a digital comparator, the responses are different. the ovlo and uvlo levels are meant to be secondary thresholds above and below the ov and uv thresholds. uvlo and ovlo ovlo and uvlo, because they provide a secondary safety condition, can cause the pack to shut down, either permanently, as is the case of an ovlo when the psd pin connects to an external fuse; or severely, as is the case of an uvlo when the device powers down and requires connection to a charger to recover. the ovlo condition can be overridden by setting the ovlo threshold to fffh or by an external c setting the cscan bit to override the internal automatic scan, then turning on the cfet. however, if the c takes permanent control of the scan, the c needs to take over the scan for a ll cells and all control functions, including comparisons of the cell voltage to ov and uv thresholds, managing time delays and controlling all cell balance functions. the uvlo response can be overridden by setting the uvlo threshold to 0v. the device can respond to the uvlo condition by entering the power down mode (set uvlopd in eeprom to ?1?) or by turning off the fets and setting the uvlo bit (uvlopd = ?0?). when the uvlopd bit is set to ?1? (indicating that the isl94203 should power down during a uvlo condition) and the cfet bit is set to ?1? (indicating that the c is in control of the fets), the automatic uvlo control forces a power-down condition, overriding the c fet control. the uvlo and ovlo detection both have delays of 5 sample cycles (typically 160ms) to prevent noise generated entry into the mode. the ovlo and uvlo values are each set by 12-bit values in eeprom. the ovlo has a recovery threshold of ovr and uvlo has a recovery threshold of uvr (if th e response overrides have been set.) if the response overrides are not set, then the recovery thresholds are usually irrelevant, for example when the uvlo forces the device into a power down condition or the ovlo condition caused a psd controlled fuse to blow. uv, ov and sleep uv, ov and slp thresholds are set by individual 12-bit values. uv and ov recovery thresholds are set by individual 12-bit values. the voltage protection scan occurs once every 32ms in normal operation. if there has been no activity (no charge or discharge current) detected in a programmable period of 1 to 16 minutes, then the scan occurs every 256ms (idle mode). if no charge or discharge condition has been detected in idle mode for a the programmable period, then the scan occurs every 512ms. if an overvoltage, undervoltage or sleep condition is detected and is pending, the scan rate remains unchanged. it can take longer to detect the fault condition in idle or doze modes. the scan rate is determined by the mode of operation and the mode of operation is determined solely by the time since pack charge/discharge current was detected. input mux/ figure 24. block diagram of cell voltage capture level digital cal eeprom 12 voltage buffer s vc0 vc1 shifter vc7 vc8 voltage buffer ram register address: [91h:90h] + 2(n-1); [ao3:ao0] (x 3/8) 1.8v vss ram register 12-bit value 14-bit value 14-bit adc output cell voltage trim address address: [abh:aah] voltage select bits 14-bit adc (n = cell number)
isl94203 33 fn7626.4 august 17, 2015 submit document feedback during a scan, each cell is monitored for overvoltage, undervoltage and sleep voltag e. the voltage will also be converted to an adc value and be stored in memory. if, during the scan, a voltage is outside the set limit, then a timer starts. there is one timer for all of the cells. if the condition remains on any cell or combination of cells for the duration of the time period, an error condition exists. this sets the appropriate flag and notifies the protection circuitry to take action (if automatic action is enabled). the time out delays for ov, uv and sleep are each 12-bit values stored in eeprom (see table 7 ). the control logic for overvolt age, undervoltage and sleep conditions is shown in table 7 and figures 25 and 26 . overvoltage detection/response the device needs to monitor the voltage on each battery cell (v cn ). if for any cell, [v cn - vc(n-1)] > v ov for a time exceeding t ov , the device sets an ov flag. then (if cfet = 0), the isl94203 turns the charge fet off, by setting the cfet bit to ?0?. once the ov flag is set the pack has ente red overcharge protection mode. the status of the discharge fet remains unaffected. the charge fet remains off until the voltage on the overcharged cell drops back below a recovery level, v ovr , for a recovery time period, t ovr . the t ovr time equals the t ov time. note: the detection timer and re covery timer are asynchronous to the voltage threshold. as a result , a setting of 1s can result in a delay time of 1s to 2s, depending on when the ov/ovr is detected. for a setting of 1000ms, the detection time will be within 1ms. the device further continues to monitor the battery cell voltages and is released from overcharge protection mode when [v cn - vc(n-1)] < v ovr for more than the overcharge release time, for all cells. when the device is released from overcharge protection mode, the charge fet is automatically sw itched on (if cfet = 0). when the device returns from overcharge protection mode, the status of the discharge fet remains unaffected. during charge, if the voltage on any cell exceeds an end of charge threshold (eocs) then an eochg bit is set and the eoc table 7. ov, uv, sleep delay times scale value delay (10-bit value) 00 0 to 1024s 01 0 to 1024ms 10 0 to 1024s 11 0 to 1024min vcn ov bit normal operation mode overcharge v ov v ovr t ov protection mode pack charge t ovr dflg set dflg reset cfet figure 25. overvoltage protection mode-event diagram dfet veoc eoc pin v ovlo psd pin ovlo bit sd pin eochg bit overvoltage lock-out protection mode normal operation mode current discharge cflg reset cfodov flag = 1 allows cfet to turn on duri ng ov, if discharging
isl94203 34 fn7626.4 august 17, 2015 submit document feedback output is pulled low. the eochg bit and the eoc output resume normal conditions when the voltage on all cells drops back below the [eocs - 117mv] threshold. there is also an overvoltage lockou t. when this level is reached, an ovlo bit is set, the psd output is set and the charge fet or precharge fet is immediately turned off (by setting the cfet or pcfet bit to ?0?). the psd output can be used to blow a fuse to protect the cells in the pack. if, during an ov condition, the cfet bit is set to ?1?, the microcontroller must control both turn off and turn on of the charge and precharge power fets. this does not apply to the ovlo condition. the device includes an option to turn the charge fet back on in an overvoltage condition, if there is discharge current flowing out of the pack. this option is set by the cfodov (cfet on during overvoltage) flag stored in eeprom. then, if the discharge current stops and there is still an overcharge condition on the cell, the device again disables the charge fet. undervoltage detection/response if v cn < v uv , for a time exceeding t uvt , the cells are said to be in a over discharge (undervoltage) state. in this condition, the isl94203 sets a uv bit. if the cfet bit is set to ?0?, the isl94203 also switches the disc harge fet off (by setting the dfet bit = ?0?). while any cell voltage is less than a low voltage charge threshold and if the pcfete bit is set, the pcfet output is turned on instead of the cfet output. this enables a precharge condition to limit the charge current to undervoltage cells. from the undervoltage mode, if the cells recover to above a v uvr level for a time exceeding t uvt plus three seconds, the isl94203 pulses the ldmon output once every 256ms and looks for the vc uv bit t uv v uvr v uv figure 26. undervoltage prot ection mode-event diagram i pack discharge lmon_en bit ldmon pin v ldmon dfet bit ld_prsnt bit v sl t sl discharge t uv cfet bit in_slp bit sleep charge? cmon_en bit chmon pin v wkupl v wkupc pcfet bit (starts looking for charger/load connect) dfet on if charging and dfoduv bit is set if pcfete set, pcfet turns on here, not cft v lvch uv bit (cfet =1) (cfet =0) v uvlo uvlo bit reset when microcontroller w rites clr_lerr bit = 1 (from c) t uv +3s dfet remains set if uvlopd = 0 and cfet = 1 uvlo set if uvlopd = 0. if uvlopd = 1 and cfet = 0 or 1, device powers down dfet on if charging and dfoduv bit is set sampling for load release (looking for tool trigger release) (clmon pulses) (clmon bit = 1) microcontroller only. load released overdischarge protection mode overdischarge protection mode t uv +3s wake up charge connect
isl94203 35 fn7626.4 august 17, 2015 submit document feedback absence of a load. the pulses are of programmable duration (0ms to 15ms) using the [lpw3: lpw0] bits. during the pulse period, a small current (~60 a) is output into the load. if there is no load, then the ldmon voltage will be higher than the recovery threshold of 0.6v. when the load has been removed and the cells are above the undervoltage recovery level, the isl94203 clears the uv bit and (if cfet = 0) turns on the discharge fet and resumes normal operation. note: the t uv detection timer and t uvr recovery timer are asynchronous to the voltage threshol d. as a result, a setting of 1s can result in a delay time of 1s to 2s (and a recovery time of 3s to 4s), depending on when the uv/uvr is detected. for a setting of 1000ms, the detection time will be within 1ms. if any of the cells drop below a sleep threshold (vcn < v slp ) for a period of time (t slt ), the device sets the sleep bit and (if cfet = 0) the isl94203 turns off the both fets (dfet and cfet = ?0?) and puts the pack into a sleep mode by setting the sleep bit to ?1?. if the cfet bit is set, the device does not go to sleep. there is also an undervoltage lock out condition. this is detected by comparing the cell voltages to a programmable uvlo threshold. when any cell voltage drops below the uvlo threshold and remains below the threshold for 5 voltage scan periods (~160ms), a uvlo bit is set and the sd output pin goes active. if uvlopd = 0 and cfet = 0, the dfet is also turned off. if uvlopd = 1, then the isl94203 goes into a power-down state. if the cfet bit is set to ?1?, th e microcontroller must both turn off and turn on the discharge power fets and control the sleep and power-down conditions. the device includes an option to turn the discharge fet back on, in an undervoltage condition, if there is a charge current flowing into the pack. this option is set by the dfoduv (dfet on during undervoltage) flag stored in eeprom. then, if the charge current stops and there is still an undervoltage condition on the cell, the device again disables the discharge fet. temperature monitoring/response as part of the normal voltage scan, the isl94203 monitors both the temperature of the device and the temperature of two external temperature sensors. external temperature 2 can be used to monitor the temperature of the fets, instead of the cells, by setting the xt2m bit to ?1?. the temperature voltages have two gain settings (the same gain for all temperature inputs). for external temperatures, a tgain bit = 0, sets the gain to 2x (ful l scale input voltage = 0.9v), see figure 27a . a tgain bit = 1 and sets the gain to 1x (full scale input voltage = 1.8v). see figure 27b . the default temperature gain setting is x2, so the temperature monitoring circuit of figure 27a is preferred. this configuration has other advantages. the temperat ure response is more linear and covers a wider temperature range before nearing the limits of the adc reading. the internal temperature reading converts from voltage to temperature using equations 1 and 2 : if the temperature of the ic (internal temp) goes above a programmed over-temperature threshold, then the isl94203 sets an over-temp flag (iot), prevents cell balancing and turns off the fets . over-temperature if the temperature of either of the external temperature sensors (xt1 or xt2), as determined by an external resistor and thermistor, goes below any of the thresholds (charge, discharge and cell balance as set by internal eeprom values), indicating an over-temperature conditio n, the isl94203 sets the corresponding over-temp flag. if the automatic responses are enabled (cfet = 0); then if the charge over-temp (cot) or discharg e over-temp flag (dot) flag is set, the corresponding charge or discharge fet is turned off. if the cell balance over-temp flag (cbot) is set, the device turns off the balancing outputs and preven ts cell balancing while the condition exists. if the automatic responses are disabled (cfet = 1) then the isl94203 only sets the flags an d an external microcontroller responds to the condition. thermistors: 10k, 10k 10k xt2 pin xt1 pin tempo pin 22k 22k +80c = 0.153v +50c = 0.295v +25c = 0.463v 0c = 0.710v -40c = 0.755v xt2 pin xt1 pin tempo pin 82.5k 82.5k +80c = 0.050v +50c = 0.120v +25c = 0.270v 0c = 0.620v -40c = 1.758v murata xh103f figure 27a. t gain = 0 (gain = 2) figure 27b. t gain = 1 (gain = 1) figure 27. external temperature circuits tgain 1 = inttemp mv ?? 1000 ? 0.92635 ----------------------------------------------- - 273.15 C ictemp ? c ?? = (eq. 1) tgain 0 = inttemp mv ?? 1000 ? 1.8527 ----------------------------------------------- - 273.15 C ictemp ? c ?? = (eq. 2)
isl94203 36 fn7626.4 august 17, 2015 submit document feedback cell balance over-temp sample mode discharge over-temp charge over-temp xt1cuts xt2>cuts or xt1>duts xt2>duts or xt1>cbuts xt2>cbuts set cut bit = 1 set dut bit = 1 set cbut bit = 1 cfet = 1 cfet = 1 cfet = 1 charge shutdown turn off cfet discharge shutdown turn off dfet balance shut down turn off balancing figure 28. temperature management state machine xt1>cotr xt2>cotr or xt1>dotr xt2>dotr or xt1>cbotr xt2>cbotr xt2m = 0 cell balance discharge charge xt1 isl94203 37 fn7626.4 august 17, 2015 submit document feedback an exception to the above occurs if the xt2 sensor is configured as a fet temperature in dicator (xt2m = ?1?). in this case, the xt2 is not compared to the cell balance temperature thresholds, it is used only for power fet control. under-temperature if the temperature of either of the external temperature sensors (xt1 or xt2), as determined by an external resistor and thermistor, goes above any of the thresholds (charge, discharge and cell balance as set by internal eeprom values), indicating an under-temperature conditio n, the isl94203 sets the corresponding under-temperature flag. if the xt1 automatic responses ar e enabled (cfet = 0); then if the charge under-temperature (cut) or discharge under- temperature flag (dut) flag is set the corresponding charge or discharge fet is turned off. if the cell balance under-temperature flag (cbut) is set, the device tu rns off cell balancing outputs and prevents cell balancing. if the xt2 automatic responses are disabled (cfet = 1) then the isl94203 only sets the flags an d an external microcontroller responds to the condition. an exception to the above occurs if the xt2 sensor is configured as a fet temperature in dicator (xt2m = ?1?). in this case, the xt2 is not compared to the cell balance temperature thresholds. it is used only for power fet control). for both xt1 and xt2, when the temperature drops back within a normal operating range, the over- or under-temperature condition is reset. microcontroller read of voltages an external microcontroller can read the value of any of the internally monitored voltages independently of the normal voltage scan. to do this requires that the c first set the cscan bit. this stops the internal scan and starts the watchdog timer. if the c maintains this state, th en communication must continue and the c must manage all vo ltage and current pack control operations as well as implemen t the cell balance algorithms. however, if the cscan bit remain s set for a short period of time, the device continues to monitor voltages and control the pack operation. once the cscan bit is set, the external c writes to register 85h to select the desired voltage and to start the adc conversion (set the adcstrt bit to 1 to start an adc conversion). once the conversion is complete, the results are read from the adc registers [adcd:adc0]. the result is a 14-bit value. the adc conversion takes about 100s or the c can poll the i 2 c link waiting for an ack to indicate that the adc conversion is complete. if the cscan bit is set when the isl94203 internal scan is scheduled, then the internal scan pauses until the cscan bit is cleared and the internal scan occurs immediately. reading an adc value from the c requires the following sequence (and time) to complete: to sample more than one time (for averaging,) repeat steps 2 through 5 as many times as desi red. however, if this is a continuous operation, care must be taken to monitor other pack functions or to pause long enough for the isl94203 internal operations to collect data to control the pack. a burst of five measurements takes about 1.8ms. voltage conversions to convert from the digital value stored in the register to a ?real world? voltage, the following conversion equations should be used. the term ?hexvalue 10 ? means the binary to decimal conversion of the register value. cell voltages cell voltage = the cell voltage conversion equation is also used to set the voltage thresholds. pack current pack current = gain is the gain setting in regist er 85h, set by the [cg1:cg0] bits. sense r is the sense resistor value in ohms. this pack current reading is valid only when the current direction indicators show that there is a ch arge or discharge current. if the current is too low for the indicators to show current flowing, then use the 14-bit value to estimate the current. see ? 14-bit register ? on page 38. temperature temperature = equation 5 converts the register value to a voltage, but the temperature then is converted to a temperature depending on the external arrangement of thermistor and resistors. see section , ? temperature monitoring/response ,? on page 35 . table 8. c controlled measurement of individual voltages step operation number i 2 c cycles time at 400khz i 2 c clk (ea.) (s) time (cumulative) (s) 1 set cscan bit 29 72.5 72.5 2 set voltage and start adc 29 72.5 145 3wait for adc complete n/a 110 255 4 read register ab 29 72.5 327.5 5 read register aa 29 72.5 410 6 clear cscan bit 29 100 472.5 hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- - (eq. 3) hexvalue 10 1.8 ? 4095 gain ? senser ? --------------------------------------------------------- - (eq. 4) hexvalue 10 1.8 ? 4095 -------------------------------------------------- (eq. 5)
isl94203 38 fn7626.4 august 17, 2015 submit document feedback 14-bit register if hexvalue 10 is greater than or equal to 8191, then 14-bit value = if hexvalue 10 is less than 8191, then 14-bit value = once the voltage value is obtained, if the measurement is a cell voltage, then the value should be multiplied by 8/3. a temperature value is used ?as-is?, but the voltage value is converted to temperature by including the external temperature circuits into the conversion. to determine pack current from this 14-bit value requires the following computations. first, if both current direction flags show zero current, then the external controller must apply an offset. measure the 14-bit voltage when there is a pack current of 0. then subtract this offset from the 14-bit current sense measurement value and take the absolute value of the re sult. if either of the current direction flags indicate a current, then do not subtract the offset value, but use the 14-bit value directly. in either case, divide the 14-bit voltage value by the current sense gain and the current sense resistor to arrive at the pack current. microcontroller fet control the external microcontroller can override the device control of the fets. with the cfet bit set to ?1?, the external microcontroller can turn the fets on or off under all conditions except the following: ? if there is a discharge short circuit condition, the device turns the fets off. the external microcontroller is responsible for turning the fets back on once the short circuit condition clears. ? if there is an internal over-temperature condition, the device turns the fets off. the external microcontroller is responsible for turning the fets back on once the temperature returns to within normal operating limits. ? if there is an overvoltage lockou t condition, the device turns the charge or precharge fets off. the external microcontroller is responsible for turning the fets back on, once the ovlo condition clears. this assumes that the psd output has not blown a fuse to disable the pack. ? if there is an open wire detection, the device turns the fets off. the external microcontroller is responsible for turning the fet back on. this assumes that the open wire did not cause the psd output to blow a fuse to disable the pack. ? if the fetsoff input is high, the fets turn off and remain off. the external c is responsible for turning the fets on once the fetsoff condition clears. ? if there is a sleep condition, the device turns the fets off. on wake up, the microcontroller is responsible for turning on the fets. the microcontroller can also co ntrol the fets by setting the cscan bit. however, this also stops the scan, requiring the microcontroller to manage the scan, voltage comparisons, fet control and cell balance. while the cscan bit is set to ?1?, the only operations controlled by the device are: ? discharge short circuit fet control. the external c cannot override the turn off of the fets during the short circuit. ? fetsoff external control. the fetsoff pin has priority on control of the fets, even when the microcontroller is managing the scan. ? in all other cases, the microcontroller must manage the fet control, because it is also ma naging the voltage scan and all comparisons. cell balance at the same rate as the scan of the cell voltages, if cell balancing is on, the system checks for proper cell balance conditions. the isl94203 prevents cell balancing if proper temperature, current and voltage conditions are not met. the cells only balance during a cbon time period. when the cboff timer is running, the cell balance is off. three additional bits determine whether the balancing happens only during charge, only during discharge, during both charge and discharge, during the end of charge condition or not at any time. ? the cell balance circuit depends on the 14-bit adc converter built into the device and the re sults of the cell voltage scan (after calibration). ? the adc converter loads a set of registers with each cell voltage during every cell voltage measurement. ? at the end of the cell voltage measurement scan, the isl94203 updates the minimum (celmin) and maximum (celmax) cell voltages. ? after calculating the celmin and celmax values, all of the cell voltages are compared with th e celmin value. when any of the cells exceed celmin by cbdl (the minimum cb delta voltage), a flag is set in ram indicating that the cell needs balancing (this is the cbnon bit). ? if any of the cells exceed the lowest cell by cbdu (maximum cb delta voltage) then a flag is set indicating that a cell voltage failure occurred (cellf). ? when the cellf flag indicates th at there is too great a cell to cell differential, the balancing is turned off. ? if celmax is below cbmin (all the cell voltages are too low for balancing) then the cbuv bit is set and there will be no cell balancing. cell balance does not start again until the cbmin value rises above (cbmin + 117mv). when this happens, the isl94203 clears the cbuv bit. hexvalue 10 16384 C ?? 1.8 ? 8191 --------------------------------------------------------------- ------------ - (eq. 6) hexvalue 10 1.8 ? 8191 -------------------------------------------------- (eq. 7)
isl94203 39 fn7626.4 august 17, 2015 submit document feedback ? if the celmin voltage is greater than the cbmax voltage (all the cell voltages are too high for balancing) then the cbov bit is set and there will be no cell balancing. cell balancing does not start again until the cbmax value drops below (cbmax - 117mv). when this happens, the isl94203 clears the cbov bit. ? a register in eeprom (cells) identifies the number of cells that are supposed to be present so only the cells present are used for the cell balance operation. note: this is also used in the cell voltage scan and op en wire detect operation. ? there are no limits to the number of cells that can be balanced at any one time, because the balancing is done external to the device. ? the cell balance block updates at the start of the cell balance on period to determine if bala ncing is needed and that the right cells are being balanced. the cells selected at this time will be balanced for the duration of the cell balance period. ? the cell balance is disabled if any external temperature is out of a programmed range set by cbuts (cell balance under temperature) and cbots (cell balance over-temperature). ? the cell balance operation can be disabled by setting the cell balance during charge (cbdc), the cell balance during discharge (cbdd) and the cell balance during end-of-charge (cb_eoc) bits to zero. see table 9 on page 39 . ? cell balancing turns off when set to balance in the charge mode and there is no charging current detected (see cb_eoc exception below). ? cell balancing turns off when set to balance in the discharge mode and there is no discharge current detected (see cb_eoc exception below). ? if cell balancing is set to operate during both charge and discharge, then isl94203 bala nces while there is charge current or discharge current, but does not balance when no current flow is detected (all other limiting factors continue to apply). see cb_eoc exception in the following. ? the cb_eoc bit provides an exception to the cell balance current direction limit. when the cb_eoc bit is set, balancing occurs while an end of charge condition exists (eoc bit = 1), regardless of current flow. this allows the isl94203 to ?drain? high voltage cells when the charge is complete. this speeds the balancing of the pack, especially when there is a large capacity differential between cells. once the end of charge condition clears, the cell balance operation returns to normal programming. ? balance is disabled by asserting the fetsoff external pin. ? the cell balance outputs are on only while the cell balance on timer is counting down. this is a 12-bit timer. the cell balance outputs are all off while the cell balance off timer is counting down. this is also a 12-bit timer. the timer values are set as in table 10 . cell balance in cascade mode when two isl94203 devices are cascaded, both devices should have the casc bit set to ?1?. when cascaded, the lower of the two devices will have an addr that is high or set to ?1?. the device with addr = 1, being on the bottom of the stack, does not monitor the current or drive the power fets. instead, they are turned off to save power consumption. table 9. cell balanc e truth table (see figure 29 ) cb_eoc bit eoc pin cbdc ching cbdd dching enable 0 1 x 1 000 0 0 0 1 x 1 000 1 0 0 1 x 1 001 0 0 0 1 x 1 001 1 1 0 1 x 1 010 0 0 0 1 x 1 010 1 0 0 1 x 1 011 0 0 0 1 x 1 011 1 0 0 1 x 1 100 0 0 0 1 x 1 100 1 0 0 1 x 1 101 0 0 0 1 x 1 101 1 1 0 1 x 1 110 0 1 0 1 x 1 110 1 0 0 1 x 1 111 0 1 0 1 x 1 111 1 0 10xxx x 1 table 10. cbon and cboff times scale value time (10-bit value) 00 0 to 1024s 01 0 to 1024ms 10 0 to 1024s 11 0 to 1024min
isl94203 40 fn7626.4 august 17, 2015 submit document feedback when casc = 1, the isl94203 does not use the current detection as part of the control algorithm for cell balancing. if all other conditions are within limit s, balancing proceeds without a detection of current. as such, balancing may happen all of the time, requiring the use of an exte rnal microcontroller to manage the algorithm. the reason for this is that there is no facility for the two cascaded devices to automatically know the cell voltages on the other device. while one device might be balancing all cells to a voltage of 3v, the other might be balancing toward a voltage of 3.2v. to simplify the microcon troller design, all scanning and protection functions operate normally. the external microcontroller needs to scan th e voltages and monitor status bits, then make decisions based on the available information and control the cell balance fets. since balancing is unrestricted, the c needs only to set the uc_does_cellbalance state to stop balancing while the upper device detects no current. c control of cell balance fets to control the cell balance fets, the external microcontroller first needs to set the ccbal bit (non-cascaded) to turn off the automatic cell balance operation. in a cascaded configuration, the external microcontroller needs to set the casc bit on the lower device. this turns off the detection of current. the external microcontroller also needs to use the ccbal bit to override the automatic cell balance operation. to turn on a cell balance fet, the c needs to turn on the cell balance output fet using the cell balance control register 84h). in this register, each bit corresponds to a specific cell balance output. with the cell balance outputs spec ified, the microc ontroller sets the cbal_on bit. this turns on the cell balance output control circuit. cell balance fet drive the cell balance fets are driven by a current source or sink of 25a. the gate voltage on the externals fet is set by the gate to source resistor. this resistor sh ould be set such that the gate voltage does not exceed 9v. an external 9v zener diode across the gate to source resistor can help to prevent overvoltage conditions on the cell balance pin. the cell balance circuit connection is shown in figure 30 . cberr cb8 driver cb7 driver cb6 driver cb5 driver cb4 driver cb3 driver cb2 driver cb1 driver figure 29. cell balance operation enable 5 6 2 4 3 1 cell5 voltage - cellmin > cbmindv or [cb5on] cell4 voltage - cellmin > cbmindv or [cb4on] cell3 voltage - cellmin > cbmindv or [cb3on] cell6 voltage - cellmin > cbmindv or [cb6on] cell7 voltage - cellmin > cbmindv or [cb7on] cell8 voltage - cellmin > cbmindv or [cb8on] cell2 voltage - cellmin > cbmindv or [cb2on] cell1 voltage - cellmin > cbmindv or [cb1on] casc cb off timer is counting cbov bit dching bit cbdd ching bit cbdc bit cb_eoc eoc fetsoff pin sd pin cellf bit open bit cbut bit cbot bit cbuv bit
isl94203 41 fn7626.4 august 17, 2015 submit document feedback watchdog timer the i 2 c watchdog timer prevents an external microcontroller from initiating an action that it cannot undo through the i 2 c port, which can result in poor or un expected operation of the pack. the watchdog timer is normally inactive when operating the device in a stand-alon e operation. when the pack is expected to have a c along with the isl94203, the wdt is activated by setting any of the following bits: cscan, ccmon, clmon, ccbal, cfet, eeen. when active (an external c is assumed to be connected), the absence of i 2 c communications for the watchdog timeout period causes a timeout event. the is l94203 needs to see a start bit and a valid slave byte to restart the timer. the watchdog timeout signal turns off the cell balance and power fet outputs, resets the serial interface and pulses the int output once per second in an at tempt to get the microcontroller to respond. if the int is unsuccessful in re-starting the communication interface, the part operates normally, except the power fets and cell balance fets are forced off. the isl94203 remains in this condition until i 2 c communications resumes. when i 2 c communication resumes, the cscan, ccmon, clmon, cfet and eeen bits ar e automatically cleared and the ccbal bit remains set. the power fets and cell balance fets turn on, if conditions allow. vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 cb7 cb6 39 vc8 cb8 100 figure 30. cell balance drive circ uits and cell connection options 10k 316k 39 1k 470nf 47nf 10k 316k 39 1k 10k 316k 47nf 39 1k 10k 316k 47nf 39 1k 10k 316k 47nf 39 1k 10k 316k 47nf 39 1k 10k 316k 47nf 39 1k 10k 316k 47nf cb5 cb4 cb3 cb2 cb1 1k 47nf vss cb6on cb7on cb8on cb5on cb4on cb3on cb2on cb1on vss 10v 10v 10v 10v 10v 10v 10v 10v 4m 4m 4m 4m 4m 4m 4m 4m isl94203 25a 25a 25a 25a 25a 25a 25a 25a cbal_on enable
isl94203 42 fn7626.4 august 17, 2015 submit document feedback power fet drive the isl94203 drives the power fets gates with a voltage higher than the supply voltage by using external capacitors as part of a charge pump. the capacitors connect (as shown in figure 2 ) and are nominally 4.7nf. the charge pump applies approximately (v dd *2) voltage to the gate, althou gh the voltage is clamped at v dd + 16v. the power fet turn-on times are limited by the capacitance of the power fet and the current supplied by the charge pump. the power fet turn-off times are limi ted by the capacitance of the power fet and the pull-down current of the isl94203. the isl94203 provides a pull-down current for up to 300s. this should be long enough to discharge any fet capacitance. table 11 shows typical turn-on and turn-off times for the isl94203 under specific conditions. general i/os there is an open drain output (sd ) that is pulled up to rgo (using an external resistor) and indi cates if there are any error conditions, such as overvoltage, undervoltage, over-temperature, open input and overcurrent. the output goes active (low) when there is any cell or pack failure condition. the output returns high when all error conditions clear. there is an open drain output (eoc ) that is pulled up to rgo (using an external resistor) and indicates that the cells have reached an end of conversion state. the output goes active (low) when all cell voltages are above a threshold specified by a 12-bit value in eeprom. the output returns high, when all cells are below the eoc threshold. factory programmable options offer inverse polarity of sd or eoc . please contact automotive marketing if there is interest in either of these options. the psd pin goes active high, wh en any cell voltage reaches the ovlo threshold (ovlo flag). optionally, psd also goes high if there is a voltage differential between any two cells that is greater than a specified limit (cellf flag) or if there is an open wire condition. this pin can be used for blowing a fuse in the pack or as an interrupt to an external c. an input pin (fetsoff), when pulled high, turns off the power fets and the cell balance fets, regardless of any other condition. higher voltage microcontrollers when using a microcontroller powe red by 3.3v or 5v, the design can include pull-up resistors to the microcontroller supply on the communication link and the open drain sd and eoc pins (instead of pull-up resistors to rgo.) the int pin is a cmos output with a maximum voltage of rgo+0.5v. it is ok to connect this directly to a microcontroller as long as the microcontroller pin does not have a pull up to the 3.3/5v supply. if it does, then a series resistor is recommended. the fetsoff input on the isl94203 is also limited to rgo+0.5v. this is limited by an input esd st ructure that clamps the voltage. the connection from the c to this pin should include a series resistor to limit any current resulting from the clamp. an example of this connection is shown in figure 31 . packs with fewer than 8 cells see ? pack configuration ? on page 20 for help when using fewer than 8 cells. this section pres ents options for minimum number of components. however, wh en using the isl94203eval1z evaluation board with fewer than 8 cells, it is not necessary to remove components from the pcb. simply tie the unused connections together, as shown in figure 32 . this normally requires only a different cable. table 11. power fet gate control (typical) parameter conditions typical power fet gate turn-on current dfet, cfet, pcfet charge pump caps = 4.7nf 32khz 5ma, pulses, 50% duty cycle power fet gate turn-on time 10% to 90% of final voltage v dd = 28v; dfet, cfet = irf1404 pcfet = fdd8451 160s 160s power fet gate turn-off current cfet, cfet, pcfet 13ma(cfet, pcfet) 15ma (dfet) power fet gate turn-off pulse width pulse duration 300s power fet gate fall time 90% to 10% of final voltage v dd = 28v; dfet: irf1404 cfet: irf1404 pcfet: fdd8451 6s 6s 2s isl94203 scl sdai sdao controller scl sda 3.3/5v figure 31. connection of high er voltage microcontroller sd eoc in_sd in_eoc int in_int * * resistor needed only if c has a pull-up on the in_int pin fetsoff out_fetsoff 10k
isl94203 43 fn7626.4 august 17, 2015 submit document feedback pc board layout the ac performance of this circuit depends greatly on the care taken in designing the pc board. the following are recommendations to achieve optimum high performance from your pc board. ? the use of low inductance comp onents, such as chip resistors and chip capacitors, is strongly recommended. ? minimize signal trace lengths. this is especially true for the cs1, cs2 and vc0-vc8 inputs. trace inductance and capacitance can easily affect circuit performance. vias in the signal lines add inductance at high frequency and should be avoided. ? match channel-to-channel analog i/o trace lengths and layout symmetry. this is especially true for the cs1 and cs2 lines, since their inputs are normally very low voltage. ? maximize use of ac decoupled pcb layers. all signal i/o lines should be routed over continuous ground planes (i.e. no split planes or ground plane gaps under these lines). avoid vias in the signal i/o lines. ? vdd bypass and charge pump capacitors should use wide temperature and high frequency dielectric (x7r or better) with capacitors rated at 2x the maximum operating voltage. 6 cells 3 cells 4 cells vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss 8 cells cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 5 cells 7 cells vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 figure 32. battery connection options using the isl94203eval1z board
isl94203 44 fn7626.4 august 17, 2015 submit document feedback ? the charge pump and vdd bypass capacitors should be located close to the isl94203 pins and vdd should have a good ground connection. ? when testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. ? an example pcb layout is shown in figure 33 . this shows placement of the vdd bypass capacitor close to the vdd pin and with a good ground co nnection. the charge pump capacitors are also close to the ic. the current sense lines are shielded by ground plane as much as possible. the ground plane under the ic is shown as an ?island?. the intent of this layout was to minimize voltages induced by emi on the ground plane in the vicinity of the ic . this example assumes a 4-layer board with most signals on the inner layers. qfn package the qfn package requires additional pcb layout rules or the thermal pad. the thermal pad is electrically connected to vss supply through the high resistance ic substrate. the thermal pad provides heat sinking for the ic. in normal operation, the device should generate little heat, so thermal pad design and layout are not too important. however, if the design uses the rgo pin to supply power to external components, then the ic can experience some internal power dissipation. in this case, careful layout of the thermal pad and the use of thermal vias to direct the heat away from the ic is an important consideration. besides heat dissipation, the thermal pad also provides noise reduction by providing a ground plane under the ic. circuit diagrams the ? block diagram ? on page 7 shows a simple application diagram with 8 cells in series and two cells in parallel (8s2p). eeprom the isl94203 contains an eeprom array for storing the device configuration parameters, the device calibration values and some user available registers. access to the eeprom is through the i 2 c port of the device. memory is organized in a memory map as described in ? registers: summary (eeprom) ? on page 49 , ? registers: summary (ram) ? on page 49 , ? registers: detailed (eeprom) ? on page 50 and ? registers: detailed (ram) ? on page 57 . when the device powers up, th e isl94203 transfers the contents of the configuration eeprom memory areas to ram (note: the user eeprom has no associated ram). an external microcontroller can read the cont ents of the configuration ram or the contents of the eeprom. prior to reading the eeprom, set the eeen bit to ?1?. this enables access to the eeprom area. if eeen is ?0?, then a read or writ e occurs in the shadow ram area. the content of the shadow ram determines the operation of the device. reading from the ram or eeprom can be done using a byte or page read. see: ? ? current address read ? on page 47 ? ? random read ? on page 47 ? ? sequential read ? on page 47 ? ? eeprom read ? on page 48 ? ? register protection ? on page 48 writing to the configuration or user eeprom must use a page write operation. each page is four bytes in length and pages begin at address 0. see: ? ? page write ? on page 46 ? ? register protection ? on page 48 the eeprom contains an error detection and correction mechanism. when reading a value from the eeprom, the device checks the data value for an error. if there are no errors, then th e eeprom value is valid and the ecc_used and ecc_fail bits are set to ?0?. if there is a 1-bit error, the isl94203 corrects the er ror and sets the ecc_used bit. this is a valid operation and va lue read from the eeprom is correct. during an eeprom read, if there is an error consisting of two or more bits, the isl9 4203 sets the ecc_fail bit (ecc_used = 0). this read contains invalid data. the error correction is also active during the initial power-on recall of the eeprom values to the shadow ram. the circuit corrects for any one-bit errors. two-bit errors are not corrected and the contents of the shadow ram ma intain the previous value. internally, the power-on recall circuit uses the ecc_used and ecc_fail bits to determine there is a proper recall before allowing the device operation to start. however, an external c cannot use these bits to detect the validity of the shadow ram on power-up or determine the use of the error correction mechanism, because the bits au tomatically reset on the next valid read. vdd cap charge pump caps gnd plane ?island ground? pink = top blue = bottom current sense inputs figure 33. example 4-layer pcb layout for vdd bypass, charge pump and current sense.
isl94203 45 fn7626.4 august 17, 2015 submit document feedback serial interface ? the isl94203 uses a standard i 2 c interface, except the design separates the sda input and output (sdai and sdao) ? separate sdai and sdao lines can be tied together and operate as a typical i 2 c bus ? interface speed is 400khz, maximum ? a separate pin is provided to select the slave address of device. this allows two devices to be cascaded serial interface conventions the device supports a bidirectio nal bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving devi ce as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the isl94203 devices operate as slaves in all applications. when sending or receiving data , the convention is the most significant bit (msb) is sent first. therefore, the first address bit sent is bit 7. clock and data data states on the sda line can change only while scl is low. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 34 ). start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met (see figure 35 ). stop condition all communications must be term inated by a stop condition, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequen ce. a stop condition is only issued after the transmitting de vice has released the bus (see figure 35 ). acknowledge acknowledge is a software convention used to indicate successful data transfer. the tran smitting device, either master or slave, releases the bus after tr ansmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge that it received the eight bits of data (see figure 36 ). the device responds with an ac knowledge after recognition of a start condition and the correct slav e byte. if a write operation is selected, the device responds with an acknowledge after the receipt of each subsequent eigh t bits. the device acknowledges all incoming data and address by tes, except for the slave byte when the contents do not match the device?s internal slave address. in the read mode, the device transmits eight bits of data, releases the sda line, then moni tor the line for an acknowledge. if an acknowledge is detected an d no stop condition is generated by the master, the device will continue to transmit data. the device terminates further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. write operations byte write for a byte write operation, the device requires the slave address byte and a word address byte. this gives the master access to any one of the words in the array. after receipt of the word address byte, the device responds with an acknowledge and awaits the next eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. the sda output is at high impedance. see figure 37 on page 46 . scl sda data stable data change data stable figure 34. valid data changes on i 2 c bus scl sda start stop figure 35. i 2 c start and stop bits 8 1 9 data output from transmitter data output from receiver start acknowledge figure 36. acknowledge response from receiver scl from master
isl94203 46 fn7626.4 august 17, 2015 submit document feedback a write to a protected block of memory suppresses the acknowledge bit. when writing to the eeprom, write to all addresses of a page without an intermediate read operation or use a page write command. each page is 4 bytes long, starting at address 0. page write a page write operation is initia ted in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. after the receipt of each byte, the device will respond with an acknowledge and the address is internally incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?rolls over? and goes back to ?0? on the same page. this means that the master can write 4 bytes to the page starting at any location on that page. if the master begins writing at location 2 and loads 4 bytes, then the first 2 bytes are written to locations 2 and 3 and the last 2 bytes are written to locations 0 and 1. afterwards, the address counter would point to location 2 of the page that was just written. if the master supplies more than 4 bytes of data, then new data overwrites the previous data, one byte at a time. see figure 38 . do not write to addresses 58h through 7fh or locations higher than address abh, since these addresses access registers that are reserved. writing to these locations can result in unexpected device operation. 0 0101 00 0 s t a r t s t o p slave byte byte address data a c k a c k a c k sda bus signals from the slave signals from the master figure 37. byte write sequence isl94203: slave byte = 50h (addr = 0) watchdog timer reset isl94203: slave byte = 52h (addr = 1) figure 38. writing 4 bytes to a 4-by te page starting at location 2 address pointer starts and ends here address = 0 data byte 3 address = 1 data byte 4 address = 2 data byte 1 address = 3 data byte 2 s t a r t s t o p slave byte register address data(1) a c k a c k a c k sda bus signals from the slave signals from the master figure 39. page write sequence data(n) a c k watchdog timer isl94203: slave byte = 50h (addr = 0) isl94203: slave byte = 52h (addr = 1)
isl94203 47 fn7626.4 august 17, 2015 submit document feedback read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address reads, random reads and sequential reads. current address read internally the device contains an address counter that maintains the address of the last word read incremented by one. therefore, if the last read was to address n, the next read operation would access data from address n+1. on power-up, the address of the address counter is undefined, requiring a read or write operation for initialization. see figure 42 . upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. the master terminates the read operation when it does not resp ond with an acknowledge during the ninth clock and then issues a stop condition. it should be noted that the ninth clock cycle of the read operation is not a ?don?t care.? to terminate a read operation, the master must either issue a stop conditio n during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. random read random read operation allows th e master to access any memory location in the array. prior to i ssuing the slave address byte with the r/w bit set to one, the master must first perform a ?dummy? write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknow ledging receipts of the word address bytes, the master immediately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition (see figure 40 ). sequential read sequential reads can be initiate d as either a current address read or random address read. the first data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. the device continues to output data for each acknowledge received. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all page and column addresses, allowing th e entire memory contents to be serially read during one operation. at the end of the address space the counter ?rolls over? to address 0000h and the device continues to output data for each acknowledge received. see figure 41 for the acknowledge and data transfer sequence. s t a r t s t o p slave byte data a c k n a c k figure 40. random read sequence s t a r t slave byte register address a c k a c k sda bus signals from the slave signals from the master a c k watchdog timer reset isl94203: slave byte = 50h (addr = 0) isl94203: slave byte = 52h (addr = 1) 0 0101 00 01 0101 00 0 1 s t o p slave byte data 1 a c k n a c k figure 41. sequential read sequence data (n) a c k data 2 a c k data (n-1) watchdog timer reset isl94203: slave byte = 50h (addr = 0) isl94203: slave byte = 52h (addr = 1) a c k
isl94203 48 fn7626.4 august 17, 2015 submit document feedback eeprom read the isl94203 has a special re quirement when reading the eeprom. an eeprom read operation from the first byte of a four byte page (locations 0h, 4h, 8h, etc.) initiates a recall of the eeprom page. this recall takes more than 200s, so the first byte may not be ready in time for a standard i 2 c response. it is necessary to either read this firs t byte of every page two times or add a loop awaiting an ack before proceeding to the next byte in the read operation. adding the wait for ack works for all read operations, so is the preferred method. synchronizing microcontroller operations with internal scan internal scans occur every 32ms in normal mode, 256ms in idle mode and 512ms in do ze mode. the internal scan normally takes about 1.3ms, with every fourth scan taking about 1.7ms. while the percentage of time taken by the scan is small, it is long enough that random communications from the microcontroller can coincide with the internal scan. when the two scans happen at the same time, errors can occur in the recorded values. to avoid errors in the recorded values, the goal is to synchronize external i 2 c transactions so that they only occur during the device?s low power state (see figure 23 on page 31 .) to assist in the synchronization, the microc ontroller can use the int_scan bit. this bit, is ?1? during the internal scan and ?0? during the ?low power state?. the microcontroller software should look for the int_scan bit to go from a ?1? to a ?0? to allow the maximum time to complete read or write operations. this insu res that the results reported to the c are from a single scan an d changes made do not interfere with state machine detection and timing. register protection the entire eeprom memory is write protected on initial power-up and during normal oper ation. an enable byte allows writing to various areas of the memory array. the enable byte is encoded, so that a value of ?0? in the eeprom enable register (89h) enables access to the shadow memory (ram), a value of ?1? allows access to the eeprom. after a read or write of the eeprom, the microcontroller should reset the eeprom enable register value back to zero to prevent inadvertent writes to the eeprom and to turn off the eeprom block to reduce current consumption. if the microcontroller fails to reset the eeprom bit and communications to the chip stops, then the watchdog timer will reset the eeprom select bit. figure 42. current address read sequence 1 0101 00 0 s t a r t s t o p slave byte data a c k n a c k a c k sda bus signals from the slave signals from the master watchdog timer reset isl94203: slave byte = 50h (addr = 0) isl94203: slave byte = 52h (addr = 1)
isl94203 49 fn7626.4 august 17, 2015 submit document feedback registers: summary (eeprom) registers: summary (ram) table 12. eeprom register summary eeprom (configured as 32 4-byte pages) page addr 0x 1x 2x 3x 4x 5x 00 overvoltage level overvoltage delay timer min cb delta charge over-temp level internal over-temp level user eeprom 1 2 overvoltage recovery undervoltage delay timer max cb delta charge over-temp recovery internal over-temp recovery 3 14 undervoltage level open wire timing cell balance on time charge under-temp level sleep voltage 5 6 undervoltage recovery discharge overcurrent timeout settings, discharge setting cell balance off time charge under-temp recovery sleep delay timer/ watchdog timer 7 28 ovlo threshold charge overcurrent timeout settings, charge overcurrent setting min cb temp level discharge over-temp level sleep mode timer reserved 9 cells config a uvlo threshold short circuit timeout settings/ recovery settings, short circuit setting min cb temp recovery discharge over-temp recovery features 1 b features 2 3c eoc voltage level min cb volts max cb temp level discharge under-temp level reserved d e low voltage charge level max cb volts max cb temp recovery discharge under-temp recovery f table 13. ram register summary ram page addr 8x 9x ax 0 0 status1 cell1 voltage it voltage 1 status2 2 status3 cell2 voltage xt1 voltage 3 status4 1 4 cell balance cell3 voltage xt2 voltage 5 analog out 6 fet cntl/override control bits cell4 voltage vbatt/16 voltage 7 override control bits 2 8 force ops cell5 voltage vrgo/2 voltage 9 ee write enable a cellmin voltage cell6 voltage 14-bit adc voltage b
isl94203 50 fn7626.4 august 17, 2015 submit document feedback registers: detailed (eeprom) 3 c cellmax voltage cell7 voltage reserved d e isense voltage cell8 voltage f table 13. ram register summary (continued) ram page addr 8x 9x ax table 14. eeprom register detail bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 076543210 00 01 overvoltage threshold if any cell voltage is above this threshold voltage for an overvoltage delay time, the charge fet is turned off. default (hex): 1e2a (v): 4.25 charge detect pulse width these bits set the duration of the charger monitor pulse width. ovlb ovla ovl9 ovl8 ovl7 ovl6 ovl5 ovl4 ovl3 ovl2 ovl1 ovl0 cpw3 cpw2 cpw1 cpw0 0000 = 0ms to 1111 = 15ms; default = 1ms 02 03 overvoltage recovery if all cells fall below this overvoltage recovery level, the charge fet is turned on. default (hex): 0dd4 (v): 4.15 reserved ovrb ovra ovr9 ovr8 ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 04 05 undervoltage threshold if any cell voltage is below this threshold voltage for an undervoltage delay time, the discharge fet is turned off. default (hex): 18ff (v): 2.7 load detect pulse width these bits set the duration of the charger monitor pulse width. uvlb uvla uvl9 uvl8 uvl7 uvl6 uvl5 uvl4 uvl3 uvl2 uvl1 uvl0 lpw3 lpw2 lpw1 lpw0 0000 = 0 ms to 1111 = 15ms; default = 1ms 06 07 undervoltage recovery if all cells rise above this overvoltage recovery level (and there is no load), the discharge fet is turned on. default (hex): 09ff v): 3.0 reserved uvrb uvra uvr9 uvr8 uvr7 uvr6 uvr5 uvr4 uvr3 uvr2 uvr1 uvr0 08 09 overvoltage lockout threshold if any cell voltage is above this thresh old for five successive scans, then the device is in an overvoltage lockout condit ion. in this condition, the charge fet is turned off, the cell balance fets are turned off, the ovlo bit is set and the psd output is set to active. default (hex): 0e7f (v): 4.35 reserved ovlob ovloa ovlo9 ovlo8 ovlo7 ovlo6 ovlo5 ovlo4 ovlo3 ovlo2 ovlo1 ovlo0 0a 0b undervoltage lockout threshold if any cell voltage is below this threshold for five successive scans, then the device is in an undervoltage lockout co ndition. in this condition, the discharge fet is turned off and the uvlo bit is set. the device also powers down (unless overridden). default (hex): 0600 (v): 1.8 reserved uvlob uvloa uvlo9 uvlo8 uvlo7 uvlo6 uvlo5 uvlo4 uvlo3 uvlo2 uvlo1 uvlo0 threshold hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- - = threshold hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- - =
isl94203 51 fn7626.4 august 17, 2015 submit document feedback 0c 0d end-of-charge (eoc) threshold if any cell exceeds this level, then the eoc output and the eoc bit are set. default (hex): 0dff (v): 4.2 reserved eocb eoca eoc9 eoc8 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0 0e 0f low voltage charge level if the voltage on any cell is less than th is level, then the pcfet output turns on instead of the pc output. to disable this function, set the value to zero or set the pcfete bit to 0. default (hex): 07aa (v): 2.3 reserved lvchb lvcha lvch9 lvch8 lvch7 lvch6 lvch5 lvch4 lvch3 lvch2 lvch1 lvch0 10 11 overvoltage delay time out this value sets the time that is required for any cell to be above the overvoltage threshold before an overvoltage condition is detected. default (hex): 0801 (s): 1 reserved ovdtb ovdta ovdt9 ovdt8 ovdt7 ovdt6 ovdt5 ovdt4 ovdt3 ovdt2 ovdt1 ovdt0 00 = s 01 = ms 10 = s 11 = min 0 to 1024 12 13 undervoltage delay time out this value sets the time that is required for any cell to be below the undervoltage threshold before an undervoltage condition is detected. default (hex): 0801 (s): 1 reserved uvdtb uvdta uvdt9 uvdt8 uvdt7 uvdt6 uvdt5 uvdt4 uvdt3 uvdt2 uvdt1 uvdt0 00 = s 01 = ms 10 = s 11 = min 0 to 1024 14 15 open wire timing (owt) this value sets the width of the open wire test pulse for each cell input. default (hex): 0214 (ms): 20 reserved owt 9 owt 8 owt 7 owt 6 owt 5 owt 4 owt 3 owt 2 owt 1 owt 0 0 = s 1 = ms 0 to 512 16 17 discharge overcurrent time out/threshold time out a discharge overcurrent needs to remain fo r this time period prior to entering a discharge overcurrent condition. this is an 12-bit value: lower 10 bits sets the time. upper bits sets the time base. default (hex): 44a0 (ms): (mv): 160 32 threshold this value sets the voltage across current sense resistor that creates a discharge overcurrent condition. ocd2 ocd1 ocd0 ocdtb ocdta ocdt9 ocdt8 ocdt7 ocdt6 ocdt5 ocdt4 ocdt3 ocdt2 ocdt1 ocdt0 000 = 4mv 001 = 8mv 010 = 16mv 011 = 24mv 100 = 32mv 101 = 48mv 110 = 64mv 111 = 96mv 00 = s 01 = ms 10 = s 11 = min 0 to 1024 table 14. eeprom register detail (continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 076543210
isl94203 52 fn7626.4 august 17, 2015 submit document feedback 18 19 charge overcurrent time out/threshold time out a charge overcurrent needs to remain for this time period prior to entering a charge overcurrent condition. this is an 12-bit value: lower 10 bits sets the time. upper bits set the time base. default (hex): 44a0 (ms): (mv): 160 8 threshold this value sets the voltage across current sense resistor that creates a charge overcurrent condition occ2 occ1 occ0 occtb occta occt9 occt8 occt7 occt6 occt5 occt4 occt3 occt2 occt1 occt0 000 = 1mv 001 = 2mv 010 = 4mv 011 = 6mv 100 = 8mv 101 = 12mv 110 = 16mv 111 = 24mv 00 = s 01 = ms 10 = s 11 = min 0 to 1024 1a 1b discharge short circuit time out/threshold time out a short circuit current needs to remain for this time period prior to entering a short circuit condition. this is an 12 bit value: lower 10 bits sets the time. upper bits set the time base default (hex): 60c8 (s): (mv): 200 128 threshold this value sets the voltage across current sense resistor that creates a short circuit condition scd2 scd1 scd0 sctb scta sct9 sct8 sct7 sct6 sct5 sct4 sct3 sct2 sct1 sct0 000 = 16mv 001 = 24mv 010 = 32mv 011 = 48mv 100 = 64mv 101 = 96mv 110 = 128mv 111 = 256mv 00 = s 01 = ms 10 = s 11 = min 0 to 1024 1c 1d cell balance minimum voltage (cbmin) if all cell voltages are less than th is voltage, then cell balance stops. default (hex): 0a55 (v): 3.1 reserved cbvlb cbvla cbvl9 cbvl8 cbvl7 cbvl6 cbvl5 cbvl4 cbvl3 cbvl2 cbvl1 cbvl0 1e 1f cell balance maximum voltage (cbmax) if all cell voltages are greater than this voltage, then cell balance stops. default (hex): 0d70 (v): 4.0 reserved cbvub cbvua cbvu9 cbvu8 cbvu7 cbvu6 cbvu5 cbvu4 cbvu3 cbvu2 cbvu1 cbvu0 20 21 cell balance minimum differential voltage (cbmindv) if the difference between the voltage on ce lln and the lowest voltage cell is less than this voltage, then cell balance for celln stops. default (hex): 0010 (mv): 20 reserved cbdlb cbdla cbdl9 cbdl8 cbdl7 cbdl6 cbdl5 cbdl4 cbdl3 cbdl2 cbdl1 cbdl0 22 23 cell balance maximum differential voltage (cbmaxdv) if the difference between the voltage on celln and the lowest voltage cell is greater than this voltage, then cell ba lance for celln stops and the cellf flag is set. default (hex): 01ab (mv): 500 reserved cbdub cbdua cbdu9 cbdu8 cbdu7 cbdu6 cbdu5 cbdu4 cbdu3 cbdu2 cbdu1 cbdu0 table 14. eeprom register detail (continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 076543210
isl94203 53 fn7626.4 august 17, 2015 submit document feedback 24 25 cell balance on time (cbon) cell balance is on for this set amount of time, unless another condition indicates that there should be no cell balance. this is a 12-bit value: lower 10 bits sets the time. upper 2 bits set the time base. default (hex): 0802 (s): 2 reserved cbont b cbont a cbont 9 cbont 8 cbont 7 cbont 6 cbont 5 cbont 4 cbont 3 cbont 2 cbont 1 cbont 0 00 = s 01 = ms 10 = s 11 = min 0 to 1024 26 27 cell balance off time (cboff) cell balance is off for the set amount of time. this is a 12-bit value: lower 10 bits sets the time. upper 2 bi ts set the time base. default (hex): 0802 (s): 2 reserved cboft b cboft a cboft 9 cboft 8 cboft 7 cboft 6 cboft 5 cboft 4 cboft 3 cboft 2 cboft 1 cboft 0 00 = s 01 = ms 10 = s 11 = min 0 to 1024 28 29 cell balance minimum temperature limit (cbuts) if the external 1 temperature or the exte rnal 2 temperature (xt2m = 0) is greater than this voltage, then cell balance st ops. the voltage is based on recommended external components (see figure 27 on page 35 ). default (hex): 0bf2 (v): (c): 1.344 -10 reserved cbuts b cbuts a cbuts 9 cbuts 8 cbuts 7 cbuts 6 cbuts 5 cbuts 4 cbuts 3 cbuts 2 cbuts 1 cbuts 0 2a 2b cell balance minimum temperature recovery level (cbutr) if the external 1 temperature and the external 2 temperature (xt2m = 0) all recover and fall below this voltage, th en cell balance can resume (all other conditions ok) .the voltage is based on recommended external components (see figure 27 on page 35 ). default (hex): 0a93 (v): (c): 1.19 +5 reserved cbutr b cbutr a cbutr 9 cbutr 8 cbutr 7 cbutr 6 cbutr 5 cbutr 4 cbutr 3 cbutr 2 cbutr 1 cbutr 0 2c 2d cell balance maximum temperature limit (cbots) if the external 1 temperature or the exte rnal 2 temperature (xt2m = 0) is less than this voltage, then cell balance st ops. the voltage is based on recommended external components (see figure 27 on page 35 ). default (hex): 04b6 (v): (c): 0.530 +55 reserved cbots b cbots a cbots 9 cbots 8 cbots 7 cbots 6 cbots 5 cbots 4 cbots 3 cbots 2 cbots 1 cbots 0 2e 2f cell balance maximum temperature recovery level (cbotr) if the external 1 temperature and the external 2 temperature (xt2m = 0) all recover and rise above this voltage, then cell balance can resume (all other conditions ok) .the voltage is based on recommended external components (see figure 27 on page 35 ). default (hex): 053e (v): (c): 0.590 +50 reserved cbotr b cbotr a cbotr 9 cbotr 8 cbotr 7 cbotr 6 cbotr 5 cbotr 4 cbotr 3 cbotr 2 cbotr 1 cbotr 0 for all temperature limits, tgain bit = 0, temperature gain = 2 30 31 charge over-temperature voltage if external 1 temperature or the external 2 temperature is less than this voltage, then the charge fet is turned off and the cot bit is set. the voltage is based on recommended external components (see figure 27 on page 35 ). default (hex): 04b6 (mv): (c): 0.530 +55 reserved cotsb cotsa cots9 cots8 cots7 cots6 cots5 cots4 cots3 cots2 cots1 cots0 table 14. eeprom register detail (continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 076543210
isl94203 54 fn7626.4 august 17, 2015 submit document feedback 32 33 charge over-temperature recovery voltage if external 1 temperature or the external 2 temperature rise above this setting, then the charge fet is turned on and the cot bit is reset (unless overrides are in place). the voltage is based on re commended external components (see figure 27 on page 35 ). default (hex): 053e (mv): (c): 0.590 +50 reserved cotrb cotra cotr9 cotr8 cotr7 cotr6 cotr5 cotr4 cotr3 cotr2 cotr1 cotr0 34 35 charge under-temperature voltage if external 1 temperature or the external 2 temperature is greater than this voltage, then the charge fet is turned off and the cut bit is set. the voltage is based on recommended external components (see figure 27 on page 35 ). default (hex): 0bf2 (mv): (c): 1.344 -10 reserved cutsb cutsa cuts9 cuts8 cuts7 cuts6 cuts5 cuts4 cuts3 cuts2 cuts1 cuts0 36 37 charge under-temperature recovery voltage if external 1 temperature or the external 2 temperature fall below this setting, then the charge fet is turned on and the cut bit is reset (unless overrides are in place). the voltage is based on re commended external components (see figure 27 on page 35 ). default (hex): 0a93 (mv): (c): 1.190 +5 reserved cutrb cutra cutr9 cutr8 cutr7 cutr6 cutr5 cutr4 cutr3 cutr2 cutr1 cutr0 38 39 discharge over-temperature voltage if external 1 temperature or the external 2 temperature is less than this voltage, then the discharge fet is turned off and the dot bit is set. the voltage is based on recommended external components (see figure 27 on page 35 ). default (hex): 4b6 (mv): (c): 0.530 +55 reserved dotsb dotsa dots9 dots8 dots7 dots6 dots5 dots4 dots3 dots2 dots1 dots0 3a 3b discharge over-temperature recovery voltage if external 1 temperature or the external 2 temperature rise above this setting, then the discharge fet is turned on and the dot bit is reset (unless overrides are in place). the voltage is based on re commended external components (see figure 27 on page 35 ). default (hex): 053e (mv): (c): 0.590 +50 reserved dotrb dotra dotr9 dotr8 dotr7 dotr6 dotr5 dotr4 dotr3 dotr2 dotr1 dotr0 3c 3d discharge under-temperature voltage if external 1 temperature or the external 2 temperature is greater than this voltage, then the discharge fet is turned off and the dut bit is set. the voltage is based on recommended external components (see figure 27 on page 35 ). default (hex): 0bf2 (mv): (c): 1.344 -10 reserved dutsb dutsa duts9 duts8 duts7 duts6 duts5 duts4 duts3 duts2 duts1 duts0 3e 3f discharge under-temperature recovery voltage if external 1 temperature or the external 2 temperature fall below this setting, then the discharge fet is turned on and the dut bit is reset (unless overrides are in place). the voltage is based on re commended external components (see figure 27 on page 35 ). default (hex): 0a93 (mv): (c): 1.190 +5 reserved dutrb dutra dutr9 dutr8 dutr7 dutr6 dutr5 dutr4 dutr3 dutr2 dutr1 dutr0 40 41 internal over-temperature voltage if the internal temperature is greater than this voltage, then all fets are turned off and the iot bit is set. default (hex): 67ch (mv): (c): 0.73 +115 reserved iots b iots a iots 9 iots 8 iots 7 iots 6 iots 5 iots 4 iots 3 iots 2 iots 1 iots 0 42 43 internal over-temperature recovery voltage when the internal temperature voltage drop s below this level, then the fets can be turned on again and the iot bit is reset on the next c read. default (hex): 621h (mv): (c): 0.69 +95 reserved iotr b iotr a iotr 9 iotr 8 iotr 7 iotr 6 iotr 5 iotr 4 iotr 3 iotr 2 iotr 1 iotr 0 table 14. eeprom register detail (continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 076543210
isl94203 55 fn7626.4 august 17, 2015 submit document feedback 44 45 sleep level voltage if any cell voltage is below this threshold voltage for a sleep delay time, the device goes into the sleep mode. default (hex): 06aa (v): 2.0 reserved sllb slla sll 9 sll 8 sll 7 sll 6 sll 5 sll 4 sll 3 sll 2 sll 1 sll 0 46 47 sleep delay timer/watchdog timer sleep delay this value sets the time that is required for any cell to be below the sleep voltage threshold before the device enters the sl eep mode. lower 10 bits sets the time. upper 1 bit sets the time base. default (hex): fc0f sleep wdt (s) (s) 1 31 watchdog timer (wdt) time allowed the microcontroller between i 2 c slave byte writes to the isl94203 after setting any override bit. wdt4 wdt3 wdt2 wdt1 wdt0 slta slt9 slt8 slt7 slt6 slt5 slt4 slt3 slt2 slt1 slt0 0 to 31 seconds 00 = s 01 = ms 10 = s 11 = min 0 to 511 48 49 sleep mode timer/cell configuration mode timer time required to enter sleep mode from the doze mode when no current is detected. default (hex): 83ff idle/ doze: sleep mode (min) (min) cells 16 240 3 cell configuration only these combinations are acceptable. any other combination will prevent any fet from turning on. cell8 cell7 cell6 cell5 cell4 cell3 cell2 cell1 mod7 mod6 mod5 mod4 mod3 mod2 mod1 mod0 8 7 6 5 4 3 2 1 number of cells idle and doze mode: [mod3:0] = 0 to 16 minutes sleep mode [mod7:0] = 0 to 240 minutes example: value = 0101 1010 idle/doze = 10 minutes sleep = 90 minutes 1 0 0 0 0 0 1 1 3 cells connected 1 1 0 0 0 0 1 1 4 cells connected 1 1 0 0 0 1 1 1 5 cells connected 1 1 1 0 0 1 1 1 6 cells connected 1 1 1 0 1 1 1 1 7 cells connected 1 1 1 1 1 1 1 1 8 cells connected table 14. eeprom register detail (continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 076543210
isl94203 56 fn7626.4 august 17, 2015 submit document feedback table 15. eeprom register detail (feature controls) bit/ addr76543210 4a cfpsd cellf psd 1 = activates psd output when a ?cell fail? condition occurs. 0 = does not activate psd output when a cell fails condition occurs. reserved xt2m xtemp 2 mode control 1 = xt2 monitors fet temp. cell balance outputs are not shut off when xt2 temperature exceeds cell balance limits 0 = xt2 monitors cell temp. (normal operation.) tgain external temp gain 1= gain of it, xt1 and xt2 inputs is 1x. 0 = gain of it, xt1 and xt2 inputs is 2x. casc two devices cascaded 1 = the device is cascaded with another device. as such, the cell balance function is disabled. 0 = there is only one device in the system. pcfete precharge fet enable 1 = precharge fet output turns on instead of the cfet output when any of the cell voltages are below the under the lvchg threshold. 0= precharge fet is not used dowd disable open wire scan 1 = disable the input open wire detection scan 0 = enable the input open wire detection scan owpsd open wire psd 1 = responds automatically to the input open wire condition and sets psd. 0 = responds automatically to the input open wire condition and does not set psd. 4b cbdd cb during discharge 1 = do balance during discharge 0 = no balance during discharge when both cbdd and cbdc equal ?0?, cell balance is turned off. cbdc cb during charge 1 = do balance during charge 0 = no balance during charge when both cbdd and cbdc equal ?0?, cell balance is turned off. dfoduv dfet on during uv (charging) 1 = keep dfet on while the pack is charging, regardless of the cell voltage. this minimizes dfet power dissipation during uv, when the pack is charging 0 = normal dfet operation. cfodov cfet on during ov (discharging) 1 = keep cfet on while the pack is discharging, regardless of the cell voltage. this minimizes cfet power dissipation during ov, when the pack is discharging 0 = normal cfet operation. uvlopd enable uvlo power-down 1 = the device powers down when detecting an uvlo condition. 0 = when a uvlo condition is detected, the device remains powered. reserved reserved cb_eoc enable cbal during eoc 1= cell balance occurs during eoc condition regardless of current direction. 0 = cell balance turns off during eoc if there is no current flowing. 4c 4f reserved 50 57 user eeprom available to the user (note: there is no shad ow memory associated with these registers).
isl94203 57 fn7626.4 august 17, 2015 submit document feedback registers: detailed (ram) table 16. ram register detail (status and control) bit/ addr 7 6 5 4 3 2 1 0 80 (read only) these bits are set and reset by the device. cut charge under temp an external thermistor shows the temp is lower than the min charge temp limit. cot charge over-temp an external thermistor shows the temp is higher than the max charge temp limit. dut discharge under-temp an external thermistor shows the temp is lower than the min discharge temp limit. dot discharge over-temp an external thermistor shows the temp is higher than the max discharge temp limit. uvlo undervoltage lockout at least one cell is below the undervoltage lockout threshold. uv undervoltage at least one cell has an undervoltage condition. ovlo overvoltage lockout at least one cell is above the overvoltage lockout threshold. ov overvoltage at least one cell has an overvoltage condition. 81 (read only) these bits are set and reset by the device eochg end of charge end of charge voltage reached. reserved open open wire an open input circuit is detected. cellf cell fail indicates that there is more than the maximum allowable voltage difference between cells. dsc discharge short circuit short circuit current detected. doc discharge overcurrent excessive discharge current detected. coc charge overcurrent excessive charge current detected. iot internal over-temp the internal sensor indicates an over-temperature condition. 82 (read only) these bits are set and reset by the device lvchg low voltage charge at least one cell voltage < lvchg threshold. if set, pcfet turns on instead of cfet. int_scan internal scan in-progress when this bit is ?1? for the duration of the internal scan. ecc_fail eeprom error correct fail eeprom error correction failed. two bits failed, error not corrected. previous value retained. ecc_used eeprom error correct eeprom error correction used. one bit failed, bit error corrected. dching discharging indicates that a discharge current is detected. charge current is flowing out of the pack. ching charging indicates that a charge current is detected. charge current is flowing into the pack. ch_prsnt chrgr present set to ?1? during coc, while charger is attached. (chmon > threshold.) if clmon = ?0?, bit resets automatically. if clmon = ?1?, bit resets by c read of register. ld_prsnt load present set to ?1? during doc or dsc, while load attached. (ldmon < threshold.) if ccmon = ?0?, bit resets automatically. if ccmon = ?1?, bit resets by c read of register. 83 (read only) these bits are set and reset by the device reserved in_sleep in sleep mode no scans. rgo remains on, vref off. monitors for a charger or load connection. in_doze in doze mode scans every 512ms. in_idle in idle mode scans every 256ms cbuv cell balance undervoltage all cell voltages < the minimum allowable cell balance voltage threshold. cbov cell balance overvoltage all cell voltages > the maximum allowable cell balance voltage threshold. cbut cell balance under-temp xt1 or xt2 indicates temp < allowable cell balance low temperature threshold cbot cell balance over-temp xt1 or xt2 indicates temp > allowable cell balance high temperature threshold 84 (r/w ) cell balance fet control bits these bits control the cell balanc e when the external controller overrides the internal cell balance operation. cb8on cb7on cb6on cb5on cb4on cb3on cb2on cb1on if ccbal = 1, cbal_on = 1 and cbnon bit = 1 the cell balance fet is on. if ccbal = 0, cbal_on = 0 or cbnon bit = 0 the cell balance fet is off.
isl94203 58 fn7626.4 august 17, 2015 submit document feedback 85 (r/w ) analog mux control bits voltage monitored by adc when microcontroller overrides the internal scan operation. current gain setting current gain set when current is monitored by adc. only used when microcontroller overrides the internal scan. adc conversion start reserved adcstrt cg1 cg0 ao3 ao2 ao1 ao0 ext c sets this bit to 1 to start a conversion cg1 0 0 0 0 1 1 0 1 1 gain x50 x5 x500 x500 ao3 2 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 off vc1 vc2 vc3 vc4 vc5 vc6 vc7 ao3 2 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 vc8 pack current vbat/16 rgo/2 xt1 xt2 it off 86 (r/w ) clr_lerr clear load error 1 = resets load monitor error condition. this bit is automatically cleared. only active when ccmon = 1 lmon_en load monitor enable 1 = load monitor on 0 = load monitor off only active when clmon = 1 clr_err clear charge error 1 = resets charge monitor error condition. this bit is automatically cleared. only active when ccmon = 1 cmon_en charge monitor enable 1 = charger monitor on 0 = charger monitor off. only active when ccmon = 1 psd pack shut down 1 = psd on 0 = psd off pcfet pre-charge fet 1 = pcfet on 0 = pcfet off bit = 0 if doc or dsc, unless the automatic response is disabled by cfet bit. (28) cfet charge fet 1 = cfet on 0 = cfet off bit = 0 if coc, unless the automatic response is disabled by cfet bit. (28) dfet discharge fet 1 = dfet on 0 = dfet off bit = 0 if doc or dsc unless the automatic response is disabled by cfet bit. (28) 87 (r/w ) reserved cfet c does fet control 1 = fets controlled by external c. 0 = norm automatic fet control (31), (34) ccbal c does cell balance 1 = internal balance disabled. c manages cell balance 0=internal balance enabled. (31) clmon c does load monitor 1 = load monitor on 0 = load monitor off (31) ccmon c does charger mon 1 = charge monitor on 0 = charge monitor off (31) cscan c does scan 1 = no auto scan. system controlled by c. 0 = normal scan (31), (3333) ow_strt open wire start 1 = does one open wire scan (bit auto reset to 0) 0 = no scan only a ct i ve if dow d = 1 or cscan = 1 cbal_on cell balance on 1= (cbnon =1) outputs on 0= cell bal outputs off only active if ccbal= 1. 88 (r/w ) reserved reserved reserved reserved pdwn power-down 1 = power-down the device. 0 = normal operation sleep set sleep 1 = put device into sleep mode. 0 = normal operation doze set doze 1 = put device into doze mode. 0 = normal operation idle set idle 1 = put device into idle mode 0 = normal operation. 89 (r/w ) eeprom enable eeen reserved. these bits should be zero. 0 = ram access 1 = eeprom access table 16. ram register detail (status and control) (continued) bit/ addr 7 6 5 4 3 2 1 0
isl94203 59 fn7626.4 august 17, 2015 submit document feedback table 17. ram register detail (monitored voltages) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 076543210 8a 8b cell minimum voltage this is the voltage of the cell with the minimum voltage. reserved cellmi nb cellmi na cellmi n9 cellmi n8 cellmi n7 cellmi n6 cellmi n5 cellmi n4 cellmi n3 cellmi n2 cellmi n1 cellmi n0 8c 8d cell maximum voltage this is the voltage of the cell with the maximum voltage. reserved cellm axb cellm axa cellm ax9 cellm ax8 cellm ax7 cellm ax6 cellm ax5 cellm ax4 cellm ax3 cellm ax2 cellm ax1 cellm ax0 8e 8f pack current this is the current flowing into or out of the pack. polarity identified by ching and dching bits. reserved isnsb isnsa isns9 isns8 isns7 isns6 isns5 isns4 isns3 isns2 isns1 isns0 90 91 cell 1 voltage this is the voltage of cell1. reserved cell1 b cell1 a cell1 9 cell1 8 cell1 7 cell1 6 cell1 5 cell1 4 cell1 3 cell1 2 cell1 1 cell1 0 92 93 cell 2 voltage this is the voltage of cell2. reserved cell2 b cell2 a cell2 9 cell2 8 cell2 7 cell2 6 cell2 5 cell2 4 cell2 3 cell2 2 cell2 1 cell2 0 94 95 cell 3 voltage this is the voltage of cell3. reserved cell3 b cell3 a cell3 9 cell3 8 cell3 7 cell3 6 cell3 5 cell3 4 cell3 3 cell3 2 cell3 1 cell3 0 96 97 cell 4 voltage this is the voltage of cell4. reserved cell4 b cell4 a cell4 9 cell4 8 cell4 7 cell4 6 cell4 5 cell4 4 cell4 3 cell4 2 cell4 1 cell4 0 98 99 cell 5 voltage this is the voltage of cell5. reserved cell5 b cell5 a cell5 9 cell5 8 cell5 7 cell5 6 cell5 5 cell5 4 cell5 3 cell5 2 cell5 1 cell5 0 9a 9b cell 6 voltage this is the voltage of cell6. reserved cell6 b cell6 a cell6 9 cell6 8 cell6 7 cell6 6 cell6 5 cell6 4 cell6 3 cell6 2 cell6 1 cell6 0 hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- - hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- - hexvalue 10 1.8 ? 4095 gain ? senser ? --------------------------------------------------------- - hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- - hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- - hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- - hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- - hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- - hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- -
isl94203 60 fn7626.4 august 17, 2015 submit document feedback 9c 9d cell 7 voltage this is the voltage of cell7. reserved cell7 b cell7 a cell7 9 cell7 8 cell7 7 cell7 6 cell7 5 cell74 cell7 3 cell7 2 cell7 1 cell7 0 9e 9f cell 8 voltage this is the voltage of cell8. reserved cell8 b cell8 a cell8 9 cell8 8 cell8 7 cell8 6 cell8 5 cell8 4 cell8 3 cell8 2 cell8 1 cell8 0 a0 a1 internal temperature this is the voltage reported by the isl94203 internal temperature sensor. reserved itb ita it9 it8 it7 it6 it5 it4 it3 it2 it1 it0 a2 a3 external 1 temperature this is the voltage reported by an external thermistor divider on the xt1 pin. reserved xt1b xt1a xt19 xt18 xt17 xt16 xt15 xt14 xt13 xt12 xt11 xt10 a4 a5 external 2 temperature this is the voltage reported by an external thermistor divider on the xt2 pin. reserved xt2b xt2a xt29 xt28 xt27 xt26 xt25 xt24 xt23 xt22 xt21 xt20 a6 a7 vbatt voltage this is the voltage of pack. reserved vbb vba vb9 vb8 vb7 vb6 vb5 vb4 vb3 vb2 vb1 vb0 a8 a9 vrgo voltage this is the voltage of isl94203 2.5v regulator. reserved rgob rgoa rgo 9 rgo 8 rgo 7 rgo 6 rgo 5 rgo 4 rgo 3 rgo 2 rgo 1 rgo 0 table 17. ram register detail (monitored voltages) (continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 076543210 hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- - hexvalue 10 1.8 8 ? ? 4095 3 ? ----------------------------------------------------------- - hexvalue 10 1.8 ? 4095 -------------------------------------------------- hexvalue 10 1.8 ? 4095 -------------------------------------------------- hexvalue 10 1.8 ? 4095 -------------------------------------------------- hexvalue 10 1.8 32 ? ? 4095 --------------------------------------------------------------- hexvalue 10 1.8 2 ? ? 4095 ----------------------------------------------------------- -
isl94203 61 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7626.4 august 17, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback aa ab 14-bit adc voltage this is the calibrated voltage out of the isl94203 adc. in normal scan mode, this value is not usable, because it cannot be associated with a specific monitored voltage. however, when the c takes over the scan operations, this value can be useful. this is a 2?s complement number. reserved adc d adc c adc b adc a adc 9 adc 8 adc 7 adc 6 adc 5 adc 4 adc 3 adc 2 adc 1 adc 0 notes: 25. a ?1? written to a control or configuration bit causes the action to be taken. a ?1? read from a status bit indicates that t he condition exists. 26. ?reserved? indicates that the bit or register is reserved for future expansion. when writing to ram addresses, write a reser ved bit with the value ?0?. do not write to reserved registers at addresses 4ch through 4fh, 58h through 7fh or ach through ffh. ignore reserved bits that are returned in a read operation. 27. the in_sleep bit is cleared on initial power up, by the chmon pin going high or by the ldmon pin going low. 28. when the automatic responses are enabled, these bits are automa tically set and reset by hardware when any conditions indicat e. when automatic responses are over-ridden, an external microcontroller i 2 c write operation controls the respective fet an d a read of the register returns the current state of the fet drive output circuit (though not the actual voltage at the output pin). 29. setting eeen to 0 prior to a read or write to the eeprom area results in a read or write to the shadow memory. setting eeen to ?1? prior to a read or write from the eeprom area results in a read or write from the non-volatile array locations. 30. writes to eeprom registers require that the eeen bit be set to ?1? and all other bits in eeprom enable register set to ?0? p rior to the write operation. 31. this bit is reset when the watchdog timer is active and expires. 32. the memory is configured as 8 pages of 16 bytes. the i 2 c can perform a ?page write? to write all values on one page in a single cycle. 33. setting this bit to ?1? disables all internal voltage and temper ature scans. when set to ?1?, the external c needs to proce ss all overvoltage, undervoltage, over-temp, under temp and all cell balance operations. 34. short circuit, open wire, internal over temperature, ovlo an d uvlo faults, plus sleep and fetsoff conditions override the c fet control bit and automatically force the appropriate power fets off. table 17. ram register detail (monitored voltages) (continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 076543210 if ? hexvalue 10 8191 ? hexvalue 10 16384 C ?? 1.8 ? 8191 --------------------------------------------------------------- ------------------------- - ? ? 8191 -------------------------------------------- ?
isl94203 62 fn7626.4 august 17, 2015 submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change august 17, 2013 fn7626.4 ordering information table, page 4: changed isl94203eval1z to ISL94203EVKIT1Z february 11, 2015 fn7626.3 -updated datasheet applying intersil?s standards. -added rc circuit to vbatt in figure 1 on page 1. -moved table of contents to page 2. -in the ?pin descriptions? on page 5 for fetsoff, add the statement, ?this pin should be pulled low when inactive.? -updated vbatt pin description on page 6. -electrical specifications, page 8, ivbatt, removed "leakage" from test condition. -absolute maximum ratings, page 8. updated esd ra tings standard revision for hbm to jesd22-a114f and replaced machine model ratings with charge device model, per current jedec standards. -in figures 2, 12, 13 and 30: changed the vbatt series r to 100 and vbatt cap to ground to 470nf and the vcn cap to ground to 47nf. -updated figure 4 on page 16 to show response if ldmon and chmon are active when device enters sleep. -updated figure 7 on page 17 to show charge pump timing relative to fet turn on/off and corrected the turn on delay time. -added int_scan bit in ram location 0x82 in table 16 on page 57. the addition of the bit is not a change to the device. this bit and descriptions about its use, are provided to make use of a previously undocumented feature. -added int_scan bit to figure 23 on page 31. -moved sections ?pc board layout? and ?qfn pack age? to precede section ?eeprom? on page 44. -section , ?pc board layout,? on page 43, fourth bull et, changed ?pcb? to ?ground plane? and added new bullet ?vdd bypass and charge pump capacitors should use wide temperature and high frequency dielectric (x7r or better) and it is recommended that the rated voltage be 2x the maximum operating voltage.? added a second new bullet, ?the charge pump and vdd bypass capacitors should be located close to the isl94203 pins and vdd should have a go od ground connection.? added a third new bullet, ?an example pcb layout...? along with a new figure, figure 33. -in figure 2, added a pull-down resistor on fetsoff. -in equations 1 and 2 on page 35, reversed the tgain values. now, equation 1 is for tgain = 1 and equation 2 is for tgain = 0. -on page 38, in ?cell balance? section updated the 7th bullet by changing from ?if celmax is below cbuv? to ?if celmax is below cbmin? an d "(cbuv + 117mv)? to ?(cbmin + 117mv)?. -on page 39 in section updated the 8th bullet by changi ng from ?if the celmin voltage is greater than the cbov voltage? to ?if the celmin voltage is greate r than the cbmax voltage? and ?[cbov - 117mv]? to ?(cbmax - 117mv)?. -in table 11 on page 42, updated row1, column 3 to read ?32khz 5ma pulses, 50% duty cycle? and row 3, the power fet turn-off current was changed from ?20ma? to ?13ma (cfet, pcfet) and 15ma (dfet)?. -on page 52, cbmin: changed ?if any cell is less than this voltage? to ?if all cell voltages are less than this voltage?. -on page 52, cbmax: changed ?if any cell is greater than this voltage? to ?if all cell voltages are greater than this voltage?. -in table 16 on page 57, the description for coc is changed to read, ?excessive charge current detected? and change doc to read ?excessive discharge current detected.? -updated the about intersil verbiage -updated pod from revision 1 to revision 2 changes are as follows: ?added tolerance values? december 5, 2012 fn7626.2 initial release.
isl94203 63 fn7626.4 august 17, 2015 submit document feedback package outline drawing l48.6x6 48 lead thin quad flat no-lead plastic package rev 2, 7/14 typical recommended land pattern detail "x" side view top view bottom view located within the zone indica ted. the pin #1 i dentifier may be unless otherwise specified, tolerance: decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifie r is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the meta llized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 6.00 0.05 a b pin 1 index area (4x) 0.15 6 4.4 37 44x 0.40 4x pin #1 index area 48 6 4 .40 0.15 1 ab 48x 0.45 0.10 24 13 48x 0.20 4 0.10 c m 36 25 12 max 0.80 seating plane base plane 5 c 0 . 2 ref 0 . 00 min. 0 . 05 max. 0.10 c 0.08 c c see detail "x" ( 5. 75 typ) ( 4. 40) (48x 0 . 20) (48x 0 . 65) (44 x 0.40) 0.05 m c 6.00 0.05

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